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https://github.com/RPCS3/llvm-mirror.git
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d300f6cd3b
The FixSGPRCopies pass converts instructions to VALU when removing illegal VGPR to SGPR copies. Instructions that use SCC are changed to use VCC instead. When that happens, the pass must also change instructions that define SCC to define VCC. The pass was not changing the SCC definition when an ADDC is converted due to a input that is a VGPR to SGPR copy. But, the initial ADD insruction, which define SCC, is not converted. This causes a compilation failure due to a use of an undefined physical register. This patch adds code that inserts the SCC definition in the MoveToVALU worklist when a SCC use is converted to a VCC use. Differential Revision: https://reviews.llvm.org/D102111
1669 lines
69 KiB
LLVM
1669 lines
69 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -amdgpu-codegenprepare-expand-div64 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-IR %s
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define amdgpu_kernel void @s_test_urem_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
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; GCN-LABEL: s_test_urem_i64:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_load_dwordx2 s[12:13], s[0:1], 0xd
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; GCN-NEXT: v_mov_b32_e32 v2, 0
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; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9
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; GCN-NEXT: s_mov_b32 s7, 0xf000
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; GCN-NEXT: s_mov_b32 s6, -1
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: v_cvt_f32_u32_e32 v0, s12
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; GCN-NEXT: v_cvt_f32_u32_e32 v1, s13
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; GCN-NEXT: s_sub_u32 s2, 0, s12
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; GCN-NEXT: s_subb_u32 s3, 0, s13
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; GCN-NEXT: s_mov_b32 s4, s8
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; GCN-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1
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; GCN-NEXT: v_rcp_f32_e32 v0, v0
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; GCN-NEXT: v_mov_b32_e32 v1, 0
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; GCN-NEXT: s_mov_b32 s5, s9
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; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
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; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v0
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; GCN-NEXT: v_trunc_f32_e32 v3, v3
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; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v3
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; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
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; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3
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; GCN-NEXT: v_mul_hi_u32 v5, s2, v0
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; GCN-NEXT: v_mul_lo_u32 v4, s2, v3
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; GCN-NEXT: v_mul_lo_u32 v7, s3, v0
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; GCN-NEXT: v_mul_lo_u32 v6, s2, v0
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; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
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; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v7
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; GCN-NEXT: v_mul_hi_u32 v5, v0, v6
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; GCN-NEXT: v_mul_lo_u32 v7, v0, v4
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; GCN-NEXT: v_mul_hi_u32 v9, v0, v4
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; GCN-NEXT: v_mul_lo_u32 v8, v3, v6
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; GCN-NEXT: v_mul_hi_u32 v6, v3, v6
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; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7
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; GCN-NEXT: v_addc_u32_e32 v7, vcc, v2, v9, vcc
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; GCN-NEXT: v_mul_hi_u32 v9, v3, v4
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; GCN-NEXT: v_mul_lo_u32 v4, v3, v4
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; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v8
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; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v6, vcc
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; GCN-NEXT: v_addc_u32_e32 v6, vcc, v9, v1, vcc
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; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
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; GCN-NEXT: v_add_i32_e64 v0, s[0:1], v0, v4
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; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc
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; GCN-NEXT: v_addc_u32_e64 v4, vcc, v3, v5, s[0:1]
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; GCN-NEXT: v_mul_lo_u32 v6, s2, v4
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; GCN-NEXT: v_mul_hi_u32 v7, s2, v0
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; GCN-NEXT: v_mul_lo_u32 v8, s3, v0
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; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6
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; GCN-NEXT: v_mul_lo_u32 v7, s2, v0
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; GCN-NEXT: v_add_i32_e32 v6, vcc, v8, v6
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; GCN-NEXT: v_mul_lo_u32 v10, v0, v6
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; GCN-NEXT: v_mul_hi_u32 v12, v0, v6
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; GCN-NEXT: v_mul_hi_u32 v11, v0, v7
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; GCN-NEXT: v_mul_hi_u32 v9, v4, v7
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; GCN-NEXT: v_mul_lo_u32 v7, v4, v7
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; GCN-NEXT: v_mul_hi_u32 v8, v4, v6
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; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10
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; GCN-NEXT: v_addc_u32_e32 v11, vcc, v2, v12, vcc
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; GCN-NEXT: v_mul_lo_u32 v4, v4, v6
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; GCN-NEXT: v_add_i32_e32 v7, vcc, v10, v7
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; GCN-NEXT: v_addc_u32_e32 v7, vcc, v11, v9, vcc
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; GCN-NEXT: v_addc_u32_e32 v6, vcc, v8, v1, vcc
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; GCN-NEXT: v_add_i32_e32 v4, vcc, v7, v4
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; GCN-NEXT: v_addc_u32_e32 v6, vcc, v2, v6, vcc
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; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5
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; GCN-NEXT: v_addc_u32_e64 v3, vcc, v3, v6, s[0:1]
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; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v4
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; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
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; GCN-NEXT: v_mul_lo_u32 v4, s10, v3
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; GCN-NEXT: v_mul_hi_u32 v5, s10, v0
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; GCN-NEXT: v_mul_hi_u32 v6, s10, v3
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; GCN-NEXT: v_mul_hi_u32 v7, s11, v3
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; GCN-NEXT: v_mul_lo_u32 v3, s11, v3
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; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
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; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc
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; GCN-NEXT: v_mul_lo_u32 v6, s11, v0
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; GCN-NEXT: v_mul_hi_u32 v0, s11, v0
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; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v6
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; GCN-NEXT: v_addc_u32_e32 v0, vcc, v5, v0, vcc
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; GCN-NEXT: v_addc_u32_e32 v1, vcc, v7, v1, vcc
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; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3
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; GCN-NEXT: v_addc_u32_e32 v1, vcc, v2, v1, vcc
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; GCN-NEXT: v_mul_lo_u32 v1, s12, v1
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; GCN-NEXT: v_mul_hi_u32 v2, s12, v0
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; GCN-NEXT: v_mul_lo_u32 v3, s13, v0
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; GCN-NEXT: v_mul_lo_u32 v0, s12, v0
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; GCN-NEXT: v_add_i32_e32 v1, vcc, v2, v1
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; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v3
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; GCN-NEXT: v_sub_i32_e32 v2, vcc, s11, v1
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; GCN-NEXT: v_mov_b32_e32 v3, s13
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; GCN-NEXT: v_sub_i32_e32 v0, vcc, s10, v0
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; GCN-NEXT: v_subb_u32_e64 v2, s[0:1], v2, v3, vcc
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; GCN-NEXT: v_subrev_i32_e64 v4, s[0:1], s12, v0
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; GCN-NEXT: v_subbrev_u32_e64 v5, s[2:3], 0, v2, s[0:1]
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; GCN-NEXT: v_cmp_le_u32_e64 s[2:3], s13, v5
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; GCN-NEXT: v_subb_u32_e64 v2, s[0:1], v2, v3, s[0:1]
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; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[2:3]
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; GCN-NEXT: v_cmp_le_u32_e64 s[2:3], s12, v4
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; GCN-NEXT: v_subrev_i32_e64 v3, s[0:1], s12, v4
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; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[2:3]
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; GCN-NEXT: v_cmp_eq_u32_e64 s[2:3], s13, v5
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; GCN-NEXT: v_cndmask_b32_e64 v6, v6, v7, s[2:3]
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; GCN-NEXT: v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1]
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; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v6
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; GCN-NEXT: v_cndmask_b32_e64 v2, v5, v2, s[0:1]
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; GCN-NEXT: v_mov_b32_e32 v5, s11
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; GCN-NEXT: v_subb_u32_e32 v1, vcc, v5, v1, vcc
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; GCN-NEXT: v_cmp_le_u32_e32 vcc, s13, v1
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; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
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; GCN-NEXT: v_cmp_le_u32_e32 vcc, s12, v0
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; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
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; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s13, v1
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; GCN-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc
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; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
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; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
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; GCN-NEXT: v_cndmask_b32_e64 v2, v4, v3, s[0:1]
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; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
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; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
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; GCN-NEXT: s_endpgm
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;
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; GCN-IR-LABEL: s_test_urem_i64:
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; GCN-IR: ; %bb.0: ; %_udiv-special-cases
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; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
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; GCN-IR-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xd
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; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[8:9], s[6:7], 0
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; GCN-IR-NEXT: s_flbit_i32_b32 s10, s2
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; GCN-IR-NEXT: s_add_i32 s10, s10, 32
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; GCN-IR-NEXT: s_flbit_i32_b32 s11, s3
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; GCN-IR-NEXT: v_mov_b32_e32 v1, s10
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; GCN-IR-NEXT: s_flbit_i32_b32 s10, s6
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; GCN-IR-NEXT: v_mov_b32_e32 v0, s11
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; GCN-IR-NEXT: v_cmp_eq_u32_e64 vcc, s3, 0
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; GCN-IR-NEXT: s_add_i32 s10, s10, 32
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; GCN-IR-NEXT: s_flbit_i32_b32 s11, s7
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; GCN-IR-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc
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; GCN-IR-NEXT: v_mov_b32_e32 v0, s11
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; GCN-IR-NEXT: v_mov_b32_e32 v1, s10
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; GCN-IR-NEXT: v_cmp_eq_u32_e64 vcc, s7, 0
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; GCN-IR-NEXT: v_cndmask_b32_e32 v3, v0, v1, vcc
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; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v2, v3
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; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[0:1], s[2:3], 0
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; GCN-IR-NEXT: v_subb_u32_e64 v1, s[10:11], 0, 0, vcc
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; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[0:1]
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; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], s[8:9]
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; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], vcc
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; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[0:1]
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; GCN-IR-NEXT: s_xor_b64 s[8:9], s[0:1], -1
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; GCN-IR-NEXT: s_and_b64 s[8:9], s[8:9], vcc
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; GCN-IR-NEXT: s_and_b64 vcc, exec, s[8:9]
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; GCN-IR-NEXT: s_cbranch_vccz BB0_4
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; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
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; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 1, v0
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; GCN-IR-NEXT: v_addc_u32_e32 v5, vcc, 0, v1, vcc
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; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[0:1], v[4:5], v[0:1]
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; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 63, v0
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; GCN-IR-NEXT: v_lshl_b64 v[0:1], s[6:7], v0
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; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[0:1]
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; GCN-IR-NEXT: s_cbranch_vccz BB0_5
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; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
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; GCN-IR-NEXT: v_not_b32_e32 v2, v2
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; GCN-IR-NEXT: s_add_u32 s8, s2, -1
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; GCN-IR-NEXT: v_lshr_b64 v[6:7], s[6:7], v4
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; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, v2, v3
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; GCN-IR-NEXT: v_mov_b32_e32 v8, 0
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; GCN-IR-NEXT: s_addc_u32 s9, s3, -1
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; GCN-IR-NEXT: v_addc_u32_e64 v5, s[0:1], -1, 0, vcc
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; GCN-IR-NEXT: v_mov_b32_e32 v9, 0
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; GCN-IR-NEXT: v_mov_b32_e32 v3, 0
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; GCN-IR-NEXT: BB0_3: ; %udiv-do-while
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; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
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; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[6:7], 1
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; GCN-IR-NEXT: v_lshrrev_b32_e32 v2, 31, v1
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; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
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; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v2
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; GCN-IR-NEXT: v_or_b32_e32 v0, v8, v0
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; GCN-IR-NEXT: v_mov_b32_e32 v2, s9
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; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, s8, v6
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; GCN-IR-NEXT: v_subb_u32_e32 v2, vcc, v2, v7, vcc
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; GCN-IR-NEXT: v_ashrrev_i32_e32 v8, 31, v2
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; GCN-IR-NEXT: v_and_b32_e32 v10, s2, v8
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; GCN-IR-NEXT: v_and_b32_e32 v2, 1, v8
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; GCN-IR-NEXT: v_and_b32_e32 v11, s3, v8
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; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v4
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; GCN-IR-NEXT: v_or_b32_e32 v1, v9, v1
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; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v5, vcc
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; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5]
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; GCN-IR-NEXT: v_mov_b32_e32 v4, v8
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; GCN-IR-NEXT: v_sub_i32_e64 v6, s[0:1], v6, v10
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; GCN-IR-NEXT: v_mov_b32_e32 v5, v9
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; GCN-IR-NEXT: v_mov_b32_e32 v9, v3
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; GCN-IR-NEXT: v_subb_u32_e64 v7, s[0:1], v7, v11, s[0:1]
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; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc
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; GCN-IR-NEXT: v_mov_b32_e32 v8, v2
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; GCN-IR-NEXT: s_cbranch_vccz BB0_3
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; GCN-IR-NEXT: s_branch BB0_6
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; GCN-IR-NEXT: BB0_4:
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; GCN-IR-NEXT: v_mov_b32_e32 v0, s7
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; GCN-IR-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[0:1]
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; GCN-IR-NEXT: v_mov_b32_e32 v0, s6
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; GCN-IR-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[0:1]
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; GCN-IR-NEXT: s_branch BB0_7
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; GCN-IR-NEXT: BB0_5:
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; GCN-IR-NEXT: v_mov_b32_e32 v2, 0
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; GCN-IR-NEXT: v_mov_b32_e32 v3, 0
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; GCN-IR-NEXT: BB0_6: ; %Flow6
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; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
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; GCN-IR-NEXT: v_or_b32_e32 v0, v2, v0
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; GCN-IR-NEXT: v_or_b32_e32 v1, v3, v1
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; GCN-IR-NEXT: BB0_7: ; %udiv-end
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; GCN-IR-NEXT: v_mul_lo_u32 v1, s2, v1
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; GCN-IR-NEXT: v_mul_hi_u32 v2, s2, v0
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; GCN-IR-NEXT: v_mul_lo_u32 v3, s3, v0
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; GCN-IR-NEXT: v_mul_lo_u32 v0, s2, v0
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; GCN-IR-NEXT: s_mov_b32 s11, 0xf000
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; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v2, v1
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; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v1, v3
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; GCN-IR-NEXT: v_mov_b32_e32 v2, s7
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; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s6, v0
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; GCN-IR-NEXT: s_mov_b32 s10, -1
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; GCN-IR-NEXT: s_mov_b32 s8, s4
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; GCN-IR-NEXT: s_mov_b32 s9, s5
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; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v2, v1, vcc
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; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0
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; GCN-IR-NEXT: s_endpgm
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%result = urem i64 %x, %y
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store i64 %result, i64 addrspace(1)* %out
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ret void
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}
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define i64 @v_test_urem_i64(i64 %x, i64 %y) {
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; GCN-LABEL: v_test_urem_i64:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: v_cvt_f32_u32_e32 v4, v2
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; GCN-NEXT: v_cvt_f32_u32_e32 v5, v3
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; GCN-NEXT: v_sub_i32_e32 v6, vcc, 0, v2
|
|
; GCN-NEXT: v_subb_u32_e32 v7, vcc, 0, v3, vcc
|
|
; GCN-NEXT: v_mov_b32_e32 v14, 0
|
|
; GCN-NEXT: v_mac_f32_e32 v4, 0x4f800000, v5
|
|
; GCN-NEXT: v_rcp_f32_e32 v4, v4
|
|
; GCN-NEXT: v_mov_b32_e32 v13, 0
|
|
; GCN-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4
|
|
; GCN-NEXT: v_mul_f32_e32 v5, 0x2f800000, v4
|
|
; GCN-NEXT: v_trunc_f32_e32 v5, v5
|
|
; GCN-NEXT: v_mac_f32_e32 v4, 0xcf800000, v5
|
|
; GCN-NEXT: v_cvt_u32_f32_e32 v4, v4
|
|
; GCN-NEXT: v_cvt_u32_f32_e32 v5, v5
|
|
; GCN-NEXT: v_mul_hi_u32 v8, v6, v4
|
|
; GCN-NEXT: v_mul_lo_u32 v9, v6, v5
|
|
; GCN-NEXT: v_mul_lo_u32 v10, v7, v4
|
|
; GCN-NEXT: v_add_i32_e32 v8, vcc, v8, v9
|
|
; GCN-NEXT: v_mul_lo_u32 v9, v6, v4
|
|
; GCN-NEXT: v_add_i32_e32 v8, vcc, v8, v10
|
|
; GCN-NEXT: v_mul_lo_u32 v11, v4, v8
|
|
; GCN-NEXT: v_mul_hi_u32 v10, v4, v8
|
|
; GCN-NEXT: v_mul_hi_u32 v12, v4, v9
|
|
; GCN-NEXT: v_mul_hi_u32 v15, v5, v8
|
|
; GCN-NEXT: v_mul_lo_u32 v8, v5, v8
|
|
; GCN-NEXT: v_add_i32_e32 v11, vcc, v12, v11
|
|
; GCN-NEXT: v_mul_lo_u32 v12, v5, v9
|
|
; GCN-NEXT: v_mul_hi_u32 v9, v5, v9
|
|
; GCN-NEXT: v_addc_u32_e32 v10, vcc, v14, v10, vcc
|
|
; GCN-NEXT: v_add_i32_e32 v11, vcc, v11, v12
|
|
; GCN-NEXT: v_addc_u32_e32 v9, vcc, v10, v9, vcc
|
|
; GCN-NEXT: v_addc_u32_e32 v10, vcc, v15, v13, vcc
|
|
; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8
|
|
; GCN-NEXT: v_add_i32_e64 v4, s[4:5], v4, v8
|
|
; GCN-NEXT: v_addc_u32_e32 v9, vcc, v14, v10, vcc
|
|
; GCN-NEXT: v_addc_u32_e64 v8, vcc, v5, v9, s[4:5]
|
|
; GCN-NEXT: v_mul_lo_u32 v10, v6, v8
|
|
; GCN-NEXT: v_mul_hi_u32 v11, v6, v4
|
|
; GCN-NEXT: v_mul_lo_u32 v7, v7, v4
|
|
; GCN-NEXT: v_mul_lo_u32 v6, v6, v4
|
|
; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10
|
|
; GCN-NEXT: v_add_i32_e32 v7, vcc, v10, v7
|
|
; GCN-NEXT: v_mul_lo_u32 v12, v4, v7
|
|
; GCN-NEXT: v_mul_hi_u32 v15, v4, v6
|
|
; GCN-NEXT: v_mul_hi_u32 v16, v4, v7
|
|
; GCN-NEXT: v_mul_hi_u32 v11, v8, v6
|
|
; GCN-NEXT: v_mul_lo_u32 v6, v8, v6
|
|
; GCN-NEXT: v_add_i32_e32 v12, vcc, v15, v12
|
|
; GCN-NEXT: v_mul_hi_u32 v10, v8, v7
|
|
; GCN-NEXT: v_addc_u32_e32 v15, vcc, v14, v16, vcc
|
|
; GCN-NEXT: v_mul_lo_u32 v7, v8, v7
|
|
; GCN-NEXT: v_add_i32_e32 v6, vcc, v12, v6
|
|
; GCN-NEXT: v_addc_u32_e32 v6, vcc, v15, v11, vcc
|
|
; GCN-NEXT: v_addc_u32_e32 v8, vcc, v10, v13, vcc
|
|
; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v7
|
|
; GCN-NEXT: v_addc_u32_e32 v7, vcc, v14, v8, vcc
|
|
; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v9
|
|
; GCN-NEXT: v_addc_u32_e64 v5, vcc, v5, v7, s[4:5]
|
|
; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v6
|
|
; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
|
|
; GCN-NEXT: v_mul_lo_u32 v6, v0, v5
|
|
; GCN-NEXT: v_mul_hi_u32 v7, v0, v4
|
|
; GCN-NEXT: v_mul_hi_u32 v8, v0, v5
|
|
; GCN-NEXT: v_mul_hi_u32 v9, v1, v5
|
|
; GCN-NEXT: v_mul_lo_u32 v5, v1, v5
|
|
; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6
|
|
; GCN-NEXT: v_addc_u32_e32 v7, vcc, v14, v8, vcc
|
|
; GCN-NEXT: v_mul_lo_u32 v8, v1, v4
|
|
; GCN-NEXT: v_mul_hi_u32 v4, v1, v4
|
|
; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v8
|
|
; GCN-NEXT: v_addc_u32_e32 v4, vcc, v7, v4, vcc
|
|
; GCN-NEXT: v_addc_u32_e32 v6, vcc, v9, v13, vcc
|
|
; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v5
|
|
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v14, v6, vcc
|
|
; GCN-NEXT: v_mul_lo_u32 v5, v2, v5
|
|
; GCN-NEXT: v_mul_hi_u32 v6, v2, v4
|
|
; GCN-NEXT: v_mul_lo_u32 v7, v3, v4
|
|
; GCN-NEXT: v_mul_lo_u32 v4, v2, v4
|
|
; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5
|
|
; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7
|
|
; GCN-NEXT: v_sub_i32_e32 v6, vcc, v1, v5
|
|
; GCN-NEXT: v_sub_i32_e32 v0, vcc, v0, v4
|
|
; GCN-NEXT: v_subb_u32_e64 v4, s[4:5], v6, v3, vcc
|
|
; GCN-NEXT: v_sub_i32_e64 v6, s[4:5], v0, v2
|
|
; GCN-NEXT: v_subbrev_u32_e64 v7, s[6:7], 0, v4, s[4:5]
|
|
; GCN-NEXT: v_cmp_ge_u32_e64 s[6:7], v7, v3
|
|
; GCN-NEXT: v_subb_u32_e32 v1, vcc, v1, v5, vcc
|
|
; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[6:7]
|
|
; GCN-NEXT: v_cmp_ge_u32_e64 s[6:7], v6, v2
|
|
; GCN-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[6:7]
|
|
; GCN-NEXT: v_cmp_eq_u32_e64 s[6:7], v7, v3
|
|
; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3
|
|
; GCN-NEXT: v_subb_u32_e64 v4, s[4:5], v4, v3, s[4:5]
|
|
; GCN-NEXT: v_cndmask_b32_e64 v8, v8, v9, s[6:7]
|
|
; GCN-NEXT: v_sub_i32_e64 v9, s[4:5], v6, v2
|
|
; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
|
|
; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2
|
|
; GCN-NEXT: v_subbrev_u32_e64 v4, s[4:5], 0, v4, s[4:5]
|
|
; GCN-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc
|
|
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v1, v3
|
|
; GCN-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc
|
|
; GCN-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v8
|
|
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
|
|
; GCN-NEXT: v_cndmask_b32_e64 v6, v6, v9, s[4:5]
|
|
; GCN-NEXT: v_cndmask_b32_e64 v2, v7, v4, s[4:5]
|
|
; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc
|
|
; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
|
|
; GCN-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GCN-IR-LABEL: v_test_urem_i64:
|
|
; GCN-IR: ; %bb.0: ; %_udiv-special-cases
|
|
; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[2:3]
|
|
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
|
|
; GCN-IR-NEXT: v_ffbh_u32_e32 v4, v2
|
|
; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
|
|
; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 32, v4
|
|
; GCN-IR-NEXT: v_ffbh_u32_e32 v5, v3
|
|
; GCN-IR-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
|
|
; GCN-IR-NEXT: v_cndmask_b32_e32 v10, v5, v4, vcc
|
|
; GCN-IR-NEXT: v_ffbh_u32_e32 v4, v0
|
|
; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 32, v4
|
|
; GCN-IR-NEXT: v_ffbh_u32_e32 v5, v1
|
|
; GCN-IR-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
|
|
; GCN-IR-NEXT: v_cndmask_b32_e32 v12, v5, v4, vcc
|
|
; GCN-IR-NEXT: v_sub_i32_e32 v5, vcc, v10, v12
|
|
; GCN-IR-NEXT: v_subb_u32_e64 v6, s[6:7], 0, 0, vcc
|
|
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[5:6]
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v11, 0
|
|
; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], vcc
|
|
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[5:6]
|
|
; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v13, v11
|
|
; GCN-IR-NEXT: v_cndmask_b32_e64 v7, v1, 0, s[4:5]
|
|
; GCN-IR-NEXT: v_cndmask_b32_e64 v4, v0, 0, s[4:5]
|
|
; GCN-IR-NEXT: s_and_b64 s[4:5], s[6:7], vcc
|
|
; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
|
|
; GCN-IR-NEXT: s_cbranch_execz BB1_6
|
|
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
|
|
; GCN-IR-NEXT: v_add_i32_e32 v7, vcc, 1, v5
|
|
; GCN-IR-NEXT: v_addc_u32_e32 v8, vcc, 0, v6, vcc
|
|
; GCN-IR-NEXT: v_sub_i32_e64 v4, s[4:5], 63, v5
|
|
; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[7:8], v[5:6]
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v8, 0
|
|
; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[0:1], v4
|
|
; GCN-IR-NEXT: s_mov_b64 s[8:9], 0
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v9, 0
|
|
; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; GCN-IR-NEXT: s_xor_b64 s[10:11], exec, s[4:5]
|
|
; GCN-IR-NEXT: s_cbranch_execz BB1_5
|
|
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
|
|
; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, -1, v2
|
|
; GCN-IR-NEXT: v_lshr_b64 v[14:15], v[0:1], v7
|
|
; GCN-IR-NEXT: v_addc_u32_e32 v7, vcc, -1, v3, vcc
|
|
; GCN-IR-NEXT: v_not_b32_e32 v8, v10
|
|
; GCN-IR-NEXT: v_not_b32_e32 v9, v11
|
|
; GCN-IR-NEXT: v_add_i32_e32 v10, vcc, v8, v12
|
|
; GCN-IR-NEXT: v_addc_u32_e32 v11, vcc, v9, v13, vcc
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v12, 0
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v13, 0
|
|
; GCN-IR-NEXT: BB1_3: ; %udiv-do-while
|
|
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
|
|
; GCN-IR-NEXT: v_lshl_b64 v[14:15], v[14:15], 1
|
|
; GCN-IR-NEXT: v_lshrrev_b32_e32 v8, 31, v5
|
|
; GCN-IR-NEXT: v_or_b32_e32 v14, v14, v8
|
|
; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[4:5], 1
|
|
; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, v6, v14
|
|
; GCN-IR-NEXT: v_subb_u32_e32 v8, vcc, v7, v15, vcc
|
|
; GCN-IR-NEXT: v_or_b32_e32 v4, v12, v4
|
|
; GCN-IR-NEXT: v_ashrrev_i32_e32 v12, 31, v8
|
|
; GCN-IR-NEXT: v_and_b32_e32 v17, v12, v2
|
|
; GCN-IR-NEXT: v_and_b32_e32 v8, 1, v12
|
|
; GCN-IR-NEXT: v_and_b32_e32 v16, v12, v3
|
|
; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, 1, v10
|
|
; GCN-IR-NEXT: v_or_b32_e32 v5, v13, v5
|
|
; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, 0, v11, vcc
|
|
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[12:13], v[10:11]
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v10, v12
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v9, 0
|
|
; GCN-IR-NEXT: v_sub_i32_e64 v14, s[4:5], v14, v17
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v11, v13
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v13, v9
|
|
; GCN-IR-NEXT: v_subb_u32_e64 v15, s[4:5], v15, v16, s[4:5]
|
|
; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9]
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v12, v8
|
|
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9]
|
|
; GCN-IR-NEXT: s_cbranch_execnz BB1_3
|
|
; GCN-IR-NEXT: ; %bb.4: ; %Flow
|
|
; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
|
|
; GCN-IR-NEXT: BB1_5: ; %Flow3
|
|
; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
|
|
; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[4:5], 1
|
|
; GCN-IR-NEXT: v_or_b32_e32 v7, v9, v5
|
|
; GCN-IR-NEXT: v_or_b32_e32 v4, v8, v4
|
|
; GCN-IR-NEXT: BB1_6: ; %Flow4
|
|
; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]
|
|
; GCN-IR-NEXT: v_mul_lo_u32 v5, v2, v7
|
|
; GCN-IR-NEXT: v_mul_hi_u32 v6, v2, v4
|
|
; GCN-IR-NEXT: v_mul_lo_u32 v3, v3, v4
|
|
; GCN-IR-NEXT: v_mul_lo_u32 v2, v2, v4
|
|
; GCN-IR-NEXT: v_add_i32_e32 v5, vcc, v6, v5
|
|
; GCN-IR-NEXT: v_add_i32_e32 v3, vcc, v5, v3
|
|
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
|
|
; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc
|
|
; GCN-IR-NEXT: s_setpc_b64 s[30:31]
|
|
%result = urem i64 %x, %y
|
|
ret i64 %result
|
|
}
|
|
|
|
define amdgpu_kernel void @s_test_urem31_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
|
|
; GCN-LABEL: s_test_urem31_i64:
|
|
; GCN: ; %bb.0:
|
|
; GCN-NEXT: s_load_dword s2, s[0:1], 0xe
|
|
; GCN-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GCN-NEXT: s_lshr_b32 s4, s2, 1
|
|
; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
|
|
; GCN-NEXT: v_cvt_f32_u32_e32 v0, s4
|
|
; GCN-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GCN-NEXT: s_mov_b32 s2, -1
|
|
; GCN-NEXT: s_lshr_b32 s5, s3, 1
|
|
; GCN-NEXT: v_cvt_f32_u32_e32 v1, s5
|
|
; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0
|
|
; GCN-NEXT: s_mov_b32 s3, 0xf000
|
|
; GCN-NEXT: v_mul_f32_e32 v2, v1, v2
|
|
; GCN-NEXT: v_trunc_f32_e32 v2, v2
|
|
; GCN-NEXT: v_cvt_u32_f32_e32 v3, v2
|
|
; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1
|
|
; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
|
|
; GCN-NEXT: v_mov_b32_e32 v1, 0
|
|
; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc
|
|
; GCN-NEXT: v_mul_lo_u32 v0, v0, s4
|
|
; GCN-NEXT: v_sub_i32_e32 v0, vcc, s5, v0
|
|
; GCN-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
|
|
; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
|
|
; GCN-NEXT: s_endpgm
|
|
;
|
|
; GCN-IR-LABEL: s_test_urem31_i64:
|
|
; GCN-IR: ; %bb.0:
|
|
; GCN-IR-NEXT: s_load_dword s2, s[0:1], 0xe
|
|
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GCN-IR-NEXT: s_lshr_b32 s4, s2, 1
|
|
; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
|
|
; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s4
|
|
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GCN-IR-NEXT: s_mov_b32 s2, -1
|
|
; GCN-IR-NEXT: s_lshr_b32 s5, s3, 1
|
|
; GCN-IR-NEXT: v_cvt_f32_u32_e32 v1, s5
|
|
; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0
|
|
; GCN-IR-NEXT: s_mov_b32 s3, 0xf000
|
|
; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2
|
|
; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2
|
|
; GCN-IR-NEXT: v_cvt_u32_f32_e32 v3, v2
|
|
; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1
|
|
; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v1, 0
|
|
; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc
|
|
; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s4
|
|
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s5, v0
|
|
; GCN-IR-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
|
|
; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
|
|
; GCN-IR-NEXT: s_endpgm
|
|
%1 = lshr i64 %x, 33
|
|
%2 = lshr i64 %y, 33
|
|
%result = urem i64 %1, %2
|
|
store i64 %result, i64 addrspace(1)* %out
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @s_test_urem31_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) {
|
|
; GCN-LABEL: s_test_urem31_v2i64:
|
|
; GCN: ; %bb.0:
|
|
; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
|
|
; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xd
|
|
; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x11
|
|
; GCN-NEXT: s_mov_b32 s7, 0xf000
|
|
; GCN-NEXT: s_mov_b32 s6, -1
|
|
; GCN-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GCN-NEXT: s_lshr_b32 s2, s9, 1
|
|
; GCN-NEXT: s_lshr_b32 s0, s1, 1
|
|
; GCN-NEXT: v_cvt_f32_u32_e32 v0, s0
|
|
; GCN-NEXT: v_cvt_f32_u32_e32 v1, s2
|
|
; GCN-NEXT: s_lshr_b32 s3, s3, 1
|
|
; GCN-NEXT: v_cvt_f32_u32_e32 v4, s3
|
|
; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0
|
|
; GCN-NEXT: s_lshr_b32 s1, s11, 1
|
|
; GCN-NEXT: v_cvt_f32_u32_e32 v3, s1
|
|
; GCN-NEXT: v_mul_f32_e32 v2, v1, v2
|
|
; GCN-NEXT: v_trunc_f32_e32 v2, v2
|
|
; GCN-NEXT: v_cvt_u32_f32_e32 v5, v2
|
|
; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1
|
|
; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v4
|
|
; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
|
|
; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v5, vcc
|
|
; GCN-NEXT: v_mul_lo_u32 v0, v0, s0
|
|
; GCN-NEXT: v_mul_f32_e32 v2, v3, v2
|
|
; GCN-NEXT: v_trunc_f32_e32 v2, v2
|
|
; GCN-NEXT: v_cvt_u32_f32_e32 v5, v2
|
|
; GCN-NEXT: v_sub_i32_e32 v0, vcc, s2, v0
|
|
; GCN-NEXT: v_mad_f32 v2, -v2, v4, v3
|
|
; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v4
|
|
; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v5, vcc
|
|
; GCN-NEXT: v_mul_lo_u32 v2, v2, s3
|
|
; GCN-NEXT: v_mov_b32_e32 v1, 0
|
|
; GCN-NEXT: s_brev_b32 s0, -2
|
|
; GCN-NEXT: v_and_b32_e32 v0, s0, v0
|
|
; GCN-NEXT: v_sub_i32_e32 v2, vcc, s1, v2
|
|
; GCN-NEXT: v_and_b32_e32 v2, s0, v2
|
|
; GCN-NEXT: v_mov_b32_e32 v3, v1
|
|
; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
|
|
; GCN-NEXT: s_endpgm
|
|
;
|
|
; GCN-IR-LABEL: s_test_urem31_v2i64:
|
|
; GCN-IR: ; %bb.0:
|
|
; GCN-IR-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
|
|
; GCN-IR-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xd
|
|
; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x11
|
|
; GCN-IR-NEXT: s_mov_b32 s7, 0xf000
|
|
; GCN-IR-NEXT: s_mov_b32 s6, -1
|
|
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GCN-IR-NEXT: s_lshr_b32 s2, s9, 1
|
|
; GCN-IR-NEXT: s_lshr_b32 s0, s1, 1
|
|
; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s0
|
|
; GCN-IR-NEXT: v_cvt_f32_u32_e32 v1, s2
|
|
; GCN-IR-NEXT: s_lshr_b32 s3, s3, 1
|
|
; GCN-IR-NEXT: v_cvt_f32_u32_e32 v4, s3
|
|
; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0
|
|
; GCN-IR-NEXT: s_lshr_b32 s1, s11, 1
|
|
; GCN-IR-NEXT: v_cvt_f32_u32_e32 v3, s1
|
|
; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2
|
|
; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2
|
|
; GCN-IR-NEXT: v_cvt_u32_f32_e32 v5, v2
|
|
; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1
|
|
; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v4
|
|
; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
|
|
; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v5, vcc
|
|
; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s0
|
|
; GCN-IR-NEXT: v_mul_f32_e32 v2, v3, v2
|
|
; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2
|
|
; GCN-IR-NEXT: v_cvt_u32_f32_e32 v5, v2
|
|
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s2, v0
|
|
; GCN-IR-NEXT: v_mad_f32 v2, -v2, v4, v3
|
|
; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v4
|
|
; GCN-IR-NEXT: v_addc_u32_e32 v2, vcc, 0, v5, vcc
|
|
; GCN-IR-NEXT: v_mul_lo_u32 v2, v2, s3
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v1, 0
|
|
; GCN-IR-NEXT: s_brev_b32 s0, -2
|
|
; GCN-IR-NEXT: v_and_b32_e32 v0, s0, v0
|
|
; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, s1, v2
|
|
; GCN-IR-NEXT: v_and_b32_e32 v2, s0, v2
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v3, v1
|
|
; GCN-IR-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
|
|
; GCN-IR-NEXT: s_endpgm
|
|
%1 = lshr <2 x i64> %x, <i64 33, i64 33>
|
|
%2 = lshr <2 x i64> %y, <i64 33, i64 33>
|
|
%result = urem <2 x i64> %1, %2
|
|
store <2 x i64> %result, <2 x i64> addrspace(1)* %out
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @s_test_urem24_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
|
|
; GCN-LABEL: s_test_urem24_i64:
|
|
; GCN: ; %bb.0:
|
|
; GCN-NEXT: s_load_dword s2, s[0:1], 0xe
|
|
; GCN-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GCN-NEXT: s_lshr_b32 s4, s2, 8
|
|
; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
|
|
; GCN-NEXT: v_cvt_f32_u32_e32 v0, s4
|
|
; GCN-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GCN-NEXT: s_mov_b32 s2, -1
|
|
; GCN-NEXT: s_lshr_b32 s5, s3, 8
|
|
; GCN-NEXT: v_cvt_f32_u32_e32 v1, s5
|
|
; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0
|
|
; GCN-NEXT: s_mov_b32 s3, 0xf000
|
|
; GCN-NEXT: v_mul_f32_e32 v2, v1, v2
|
|
; GCN-NEXT: v_trunc_f32_e32 v2, v2
|
|
; GCN-NEXT: v_cvt_u32_f32_e32 v3, v2
|
|
; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1
|
|
; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
|
|
; GCN-NEXT: v_mov_b32_e32 v1, 0
|
|
; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc
|
|
; GCN-NEXT: v_mul_lo_u32 v0, v0, s4
|
|
; GCN-NEXT: v_sub_i32_e32 v0, vcc, s5, v0
|
|
; GCN-NEXT: v_and_b32_e32 v0, 0xffffff, v0
|
|
; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
|
|
; GCN-NEXT: s_endpgm
|
|
;
|
|
; GCN-IR-LABEL: s_test_urem24_i64:
|
|
; GCN-IR: ; %bb.0:
|
|
; GCN-IR-NEXT: s_load_dword s2, s[0:1], 0xe
|
|
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GCN-IR-NEXT: s_lshr_b32 s4, s2, 8
|
|
; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
|
|
; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s4
|
|
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GCN-IR-NEXT: s_mov_b32 s2, -1
|
|
; GCN-IR-NEXT: s_lshr_b32 s5, s3, 8
|
|
; GCN-IR-NEXT: v_cvt_f32_u32_e32 v1, s5
|
|
; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0
|
|
; GCN-IR-NEXT: s_mov_b32 s3, 0xf000
|
|
; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2
|
|
; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2
|
|
; GCN-IR-NEXT: v_cvt_u32_f32_e32 v3, v2
|
|
; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1
|
|
; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v1, 0
|
|
; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc
|
|
; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s4
|
|
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s5, v0
|
|
; GCN-IR-NEXT: v_and_b32_e32 v0, 0xffffff, v0
|
|
; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
|
|
; GCN-IR-NEXT: s_endpgm
|
|
%1 = lshr i64 %x, 40
|
|
%2 = lshr i64 %y, 40
|
|
%result = urem i64 %1, %2
|
|
store i64 %result, i64 addrspace(1)* %out
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @s_test_urem23_64_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) {
|
|
; GCN-LABEL: s_test_urem23_64_v2i64:
|
|
; GCN: ; %bb.0:
|
|
; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
|
|
; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xd
|
|
; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x11
|
|
; GCN-NEXT: s_mov_b32 s7, 0xf000
|
|
; GCN-NEXT: s_mov_b32 s6, -1
|
|
; GCN-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GCN-NEXT: s_lshr_b32 s2, s9, 1
|
|
; GCN-NEXT: s_lshr_b32 s0, s1, 1
|
|
; GCN-NEXT: v_cvt_f32_u32_e32 v0, s0
|
|
; GCN-NEXT: v_cvt_f32_u32_e32 v1, s2
|
|
; GCN-NEXT: s_lshr_b32 s3, s3, 9
|
|
; GCN-NEXT: v_cvt_f32_u32_e32 v4, s3
|
|
; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0
|
|
; GCN-NEXT: s_lshr_b32 s1, s11, 9
|
|
; GCN-NEXT: v_cvt_f32_u32_e32 v3, s1
|
|
; GCN-NEXT: v_mul_f32_e32 v2, v1, v2
|
|
; GCN-NEXT: v_trunc_f32_e32 v2, v2
|
|
; GCN-NEXT: v_cvt_u32_f32_e32 v5, v2
|
|
; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1
|
|
; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v4
|
|
; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
|
|
; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v5, vcc
|
|
; GCN-NEXT: v_mul_lo_u32 v0, v0, s0
|
|
; GCN-NEXT: v_mul_f32_e32 v2, v3, v2
|
|
; GCN-NEXT: v_trunc_f32_e32 v2, v2
|
|
; GCN-NEXT: v_cvt_u32_f32_e32 v5, v2
|
|
; GCN-NEXT: v_sub_i32_e32 v0, vcc, s2, v0
|
|
; GCN-NEXT: v_mad_f32 v2, -v2, v4, v3
|
|
; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v4
|
|
; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v5, vcc
|
|
; GCN-NEXT: v_mul_lo_u32 v2, v2, s3
|
|
; GCN-NEXT: v_mov_b32_e32 v1, 0
|
|
; GCN-NEXT: s_brev_b32 s0, -2
|
|
; GCN-NEXT: v_and_b32_e32 v0, s0, v0
|
|
; GCN-NEXT: v_sub_i32_e32 v2, vcc, s1, v2
|
|
; GCN-NEXT: v_and_b32_e32 v2, s0, v2
|
|
; GCN-NEXT: v_mov_b32_e32 v3, v1
|
|
; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
|
|
; GCN-NEXT: s_endpgm
|
|
;
|
|
; GCN-IR-LABEL: s_test_urem23_64_v2i64:
|
|
; GCN-IR: ; %bb.0:
|
|
; GCN-IR-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
|
|
; GCN-IR-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xd
|
|
; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x11
|
|
; GCN-IR-NEXT: s_mov_b32 s7, 0xf000
|
|
; GCN-IR-NEXT: s_mov_b32 s6, -1
|
|
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GCN-IR-NEXT: s_lshr_b32 s2, s9, 1
|
|
; GCN-IR-NEXT: s_lshr_b32 s0, s1, 1
|
|
; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s0
|
|
; GCN-IR-NEXT: v_cvt_f32_u32_e32 v1, s2
|
|
; GCN-IR-NEXT: s_lshr_b32 s3, s3, 9
|
|
; GCN-IR-NEXT: v_cvt_f32_u32_e32 v4, s3
|
|
; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0
|
|
; GCN-IR-NEXT: s_lshr_b32 s1, s11, 9
|
|
; GCN-IR-NEXT: v_cvt_f32_u32_e32 v3, s1
|
|
; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2
|
|
; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2
|
|
; GCN-IR-NEXT: v_cvt_u32_f32_e32 v5, v2
|
|
; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1
|
|
; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v4
|
|
; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
|
|
; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v5, vcc
|
|
; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s0
|
|
; GCN-IR-NEXT: v_mul_f32_e32 v2, v3, v2
|
|
; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2
|
|
; GCN-IR-NEXT: v_cvt_u32_f32_e32 v5, v2
|
|
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s2, v0
|
|
; GCN-IR-NEXT: v_mad_f32 v2, -v2, v4, v3
|
|
; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v4
|
|
; GCN-IR-NEXT: v_addc_u32_e32 v2, vcc, 0, v5, vcc
|
|
; GCN-IR-NEXT: v_mul_lo_u32 v2, v2, s3
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v1, 0
|
|
; GCN-IR-NEXT: s_brev_b32 s0, -2
|
|
; GCN-IR-NEXT: v_and_b32_e32 v0, s0, v0
|
|
; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, s1, v2
|
|
; GCN-IR-NEXT: v_and_b32_e32 v2, s0, v2
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v3, v1
|
|
; GCN-IR-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
|
|
; GCN-IR-NEXT: s_endpgm
|
|
%1 = lshr <2 x i64> %x, <i64 33, i64 41>
|
|
%2 = lshr <2 x i64> %y, <i64 33, i64 41>
|
|
%result = urem <2 x i64> %1, %2
|
|
store <2 x i64> %result, <2 x i64> addrspace(1)* %out
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @s_test_urem_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
|
|
; GCN-LABEL: s_test_urem_k_num_i64:
|
|
; GCN: ; %bb.0:
|
|
; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
|
|
; GCN-NEXT: v_mov_b32_e32 v2, 0
|
|
; GCN-NEXT: s_mov_b32 s11, 0xf000
|
|
; GCN-NEXT: s_mov_b32 s10, -1
|
|
; GCN-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GCN-NEXT: v_cvt_f32_u32_e32 v0, s6
|
|
; GCN-NEXT: v_cvt_f32_u32_e32 v1, s7
|
|
; GCN-NEXT: s_sub_u32 s2, 0, s6
|
|
; GCN-NEXT: s_subb_u32 s3, 0, s7
|
|
; GCN-NEXT: s_mov_b32 s8, s4
|
|
; GCN-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1
|
|
; GCN-NEXT: v_rcp_f32_e32 v0, v0
|
|
; GCN-NEXT: v_mov_b32_e32 v1, 0
|
|
; GCN-NEXT: s_mov_b32 s9, s5
|
|
; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
|
|
; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v0
|
|
; GCN-NEXT: v_trunc_f32_e32 v3, v3
|
|
; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v3
|
|
; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
|
|
; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3
|
|
; GCN-NEXT: v_mul_hi_u32 v5, s2, v0
|
|
; GCN-NEXT: v_mul_lo_u32 v4, s2, v3
|
|
; GCN-NEXT: v_mul_lo_u32 v7, s3, v0
|
|
; GCN-NEXT: v_mul_lo_u32 v6, s2, v0
|
|
; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
|
|
; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v7
|
|
; GCN-NEXT: v_mul_hi_u32 v5, v0, v6
|
|
; GCN-NEXT: v_mul_lo_u32 v7, v0, v4
|
|
; GCN-NEXT: v_mul_hi_u32 v9, v0, v4
|
|
; GCN-NEXT: v_mul_hi_u32 v8, v3, v6
|
|
; GCN-NEXT: v_mul_lo_u32 v6, v3, v6
|
|
; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7
|
|
; GCN-NEXT: v_mul_hi_u32 v10, v3, v4
|
|
; GCN-NEXT: v_addc_u32_e32 v7, vcc, v2, v9, vcc
|
|
; GCN-NEXT: v_mul_lo_u32 v4, v3, v4
|
|
; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v6
|
|
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v8, vcc
|
|
; GCN-NEXT: v_addc_u32_e32 v6, vcc, v10, v1, vcc
|
|
; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
|
|
; GCN-NEXT: v_add_i32_e64 v0, s[0:1], v0, v4
|
|
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc
|
|
; GCN-NEXT: v_addc_u32_e64 v4, vcc, v3, v5, s[0:1]
|
|
; GCN-NEXT: v_mul_lo_u32 v6, s2, v4
|
|
; GCN-NEXT: v_mul_hi_u32 v7, s2, v0
|
|
; GCN-NEXT: v_mul_lo_u32 v8, s3, v0
|
|
; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6
|
|
; GCN-NEXT: v_mul_lo_u32 v7, s2, v0
|
|
; GCN-NEXT: v_add_i32_e32 v6, vcc, v8, v6
|
|
; GCN-NEXT: v_mul_lo_u32 v10, v0, v6
|
|
; GCN-NEXT: v_mul_hi_u32 v12, v0, v6
|
|
; GCN-NEXT: v_mul_hi_u32 v11, v0, v7
|
|
; GCN-NEXT: v_mul_hi_u32 v9, v4, v7
|
|
; GCN-NEXT: v_mul_lo_u32 v7, v4, v7
|
|
; GCN-NEXT: v_mul_hi_u32 v8, v4, v6
|
|
; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10
|
|
; GCN-NEXT: v_addc_u32_e32 v11, vcc, v2, v12, vcc
|
|
; GCN-NEXT: v_mul_lo_u32 v4, v4, v6
|
|
; GCN-NEXT: v_add_i32_e32 v7, vcc, v10, v7
|
|
; GCN-NEXT: v_addc_u32_e32 v7, vcc, v11, v9, vcc
|
|
; GCN-NEXT: v_addc_u32_e32 v1, vcc, v8, v1, vcc
|
|
; GCN-NEXT: v_add_i32_e32 v4, vcc, v7, v4
|
|
; GCN-NEXT: v_addc_u32_e32 v1, vcc, v2, v1, vcc
|
|
; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5
|
|
; GCN-NEXT: v_addc_u32_e64 v1, vcc, v3, v1, s[0:1]
|
|
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v4
|
|
; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GCN-NEXT: v_mul_lo_u32 v3, v1, 24
|
|
; GCN-NEXT: v_mul_hi_u32 v0, v0, 24
|
|
; GCN-NEXT: v_mul_hi_u32 v1, v1, 24
|
|
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3
|
|
; GCN-NEXT: v_addc_u32_e32 v0, vcc, v2, v1, vcc
|
|
; GCN-NEXT: v_mul_lo_u32 v1, s7, v0
|
|
; GCN-NEXT: v_mul_hi_u32 v2, s6, v0
|
|
; GCN-NEXT: v_mul_lo_u32 v0, s6, v0
|
|
; GCN-NEXT: v_mov_b32_e32 v3, s7
|
|
; GCN-NEXT: v_add_i32_e32 v1, vcc, v2, v1
|
|
; GCN-NEXT: v_sub_i32_e32 v2, vcc, 0, v1
|
|
; GCN-NEXT: v_sub_i32_e32 v0, vcc, 24, v0
|
|
; GCN-NEXT: v_subb_u32_e64 v2, s[0:1], v2, v3, vcc
|
|
; GCN-NEXT: v_subrev_i32_e64 v4, s[0:1], s6, v0
|
|
; GCN-NEXT: v_subbrev_u32_e64 v5, s[2:3], 0, v2, s[0:1]
|
|
; GCN-NEXT: v_cmp_le_u32_e64 s[2:3], s7, v5
|
|
; GCN-NEXT: v_subb_u32_e64 v2, s[0:1], v2, v3, s[0:1]
|
|
; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[2:3]
|
|
; GCN-NEXT: v_cmp_le_u32_e64 s[2:3], s6, v4
|
|
; GCN-NEXT: v_subrev_i32_e64 v3, s[0:1], s6, v4
|
|
; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[2:3]
|
|
; GCN-NEXT: v_cmp_eq_u32_e64 s[2:3], s7, v5
|
|
; GCN-NEXT: v_subb_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GCN-NEXT: v_cndmask_b32_e64 v6, v6, v7, s[2:3]
|
|
; GCN-NEXT: v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1]
|
|
; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v6
|
|
; GCN-NEXT: v_cmp_le_u32_e32 vcc, s7, v1
|
|
; GCN-NEXT: v_cndmask_b32_e64 v2, v5, v2, s[0:1]
|
|
; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
|
|
; GCN-NEXT: v_cmp_le_u32_e32 vcc, s6, v0
|
|
; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
|
|
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s7, v1
|
|
; GCN-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc
|
|
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
|
|
; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
|
|
; GCN-NEXT: v_cndmask_b32_e64 v2, v4, v3, s[0:1]
|
|
; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
|
|
; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0
|
|
; GCN-NEXT: s_endpgm
|
|
;
|
|
; GCN-IR-LABEL: s_test_urem_k_num_i64:
|
|
; GCN-IR: ; %bb.0: ; %_udiv-special-cases
|
|
; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
|
|
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GCN-IR-NEXT: s_flbit_i32_b32 s2, s6
|
|
; GCN-IR-NEXT: s_flbit_i32_b32 s3, s7
|
|
; GCN-IR-NEXT: s_add_i32 s2, s2, 32
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v0, s3
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v1, s2
|
|
; GCN-IR-NEXT: v_cmp_eq_u32_e64 vcc, s7, 0
|
|
; GCN-IR-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc
|
|
; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 0xffffffc5, v2
|
|
; GCN-IR-NEXT: v_addc_u32_e64 v1, s[2:3], 0, -1, vcc
|
|
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[0:1], s[6:7], 0
|
|
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[0:1]
|
|
; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], vcc
|
|
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[0:1]
|
|
; GCN-IR-NEXT: s_xor_b64 s[2:3], s[0:1], -1
|
|
; GCN-IR-NEXT: s_and_b64 s[2:3], s[2:3], vcc
|
|
; GCN-IR-NEXT: s_and_b64 vcc, exec, s[2:3]
|
|
; GCN-IR-NEXT: s_cbranch_vccz BB6_4
|
|
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
|
|
; GCN-IR-NEXT: v_add_i32_e32 v3, vcc, 1, v0
|
|
; GCN-IR-NEXT: v_addc_u32_e32 v4, vcc, 0, v1, vcc
|
|
; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[0:1], v[3:4], v[0:1]
|
|
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 63, v0
|
|
; GCN-IR-NEXT: v_lshl_b64 v[0:1], 24, v0
|
|
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[0:1]
|
|
; GCN-IR-NEXT: s_cbranch_vccz BB6_5
|
|
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
|
|
; GCN-IR-NEXT: s_add_u32 s2, s6, -1
|
|
; GCN-IR-NEXT: v_lshr_b64 v[6:7], 24, v3
|
|
; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, 58, v2
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v8, 0
|
|
; GCN-IR-NEXT: s_addc_u32 s3, s7, -1
|
|
; GCN-IR-NEXT: v_subb_u32_e64 v5, s[0:1], 0, 0, vcc
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v9, 0
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v3, 0
|
|
; GCN-IR-NEXT: BB6_3: ; %udiv-do-while
|
|
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
|
|
; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[6:7], 1
|
|
; GCN-IR-NEXT: v_lshrrev_b32_e32 v2, 31, v1
|
|
; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
|
|
; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v2
|
|
; GCN-IR-NEXT: v_or_b32_e32 v0, v8, v0
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v2, s3
|
|
; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, s2, v6
|
|
; GCN-IR-NEXT: v_subb_u32_e32 v2, vcc, v2, v7, vcc
|
|
; GCN-IR-NEXT: v_ashrrev_i32_e32 v8, 31, v2
|
|
; GCN-IR-NEXT: v_and_b32_e32 v10, s6, v8
|
|
; GCN-IR-NEXT: v_and_b32_e32 v2, 1, v8
|
|
; GCN-IR-NEXT: v_and_b32_e32 v11, s7, v8
|
|
; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v4
|
|
; GCN-IR-NEXT: v_or_b32_e32 v1, v9, v1
|
|
; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v5, vcc
|
|
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5]
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v4, v8
|
|
; GCN-IR-NEXT: v_sub_i32_e64 v6, s[0:1], v6, v10
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v5, v9
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v9, v3
|
|
; GCN-IR-NEXT: v_subb_u32_e64 v7, s[0:1], v7, v11, s[0:1]
|
|
; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v8, v2
|
|
; GCN-IR-NEXT: s_cbranch_vccz BB6_3
|
|
; GCN-IR-NEXT: s_branch BB6_6
|
|
; GCN-IR-NEXT: BB6_4:
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v1, 0
|
|
; GCN-IR-NEXT: v_cndmask_b32_e64 v0, 24, 0, s[0:1]
|
|
; GCN-IR-NEXT: s_branch BB6_7
|
|
; GCN-IR-NEXT: BB6_5:
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v2, 0
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v3, 0
|
|
; GCN-IR-NEXT: BB6_6: ; %Flow5
|
|
; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
|
|
; GCN-IR-NEXT: v_or_b32_e32 v0, v2, v0
|
|
; GCN-IR-NEXT: v_or_b32_e32 v1, v3, v1
|
|
; GCN-IR-NEXT: BB6_7: ; %udiv-end
|
|
; GCN-IR-NEXT: v_mul_lo_u32 v1, s6, v1
|
|
; GCN-IR-NEXT: v_mul_hi_u32 v2, s6, v0
|
|
; GCN-IR-NEXT: v_mul_lo_u32 v3, s7, v0
|
|
; GCN-IR-NEXT: v_mul_lo_u32 v0, s6, v0
|
|
; GCN-IR-NEXT: s_mov_b32 s3, 0xf000
|
|
; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v2, v1
|
|
; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v1, v3
|
|
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 24, v0
|
|
; GCN-IR-NEXT: s_mov_b32 s2, -1
|
|
; GCN-IR-NEXT: s_mov_b32 s0, s4
|
|
; GCN-IR-NEXT: s_mov_b32 s1, s5
|
|
; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
|
|
; GCN-IR-NEXT: s_endpgm
|
|
%result = urem i64 24, %x
|
|
store i64 %result, i64 addrspace(1)* %out
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @s_test_urem_k_den_i64(i64 addrspace(1)* %out, i64 %x) {
|
|
; GCN-LABEL: s_test_urem_k_den_i64:
|
|
; GCN: ; %bb.0:
|
|
; GCN-NEXT: v_mov_b32_e32 v0, 0x4f800000
|
|
; GCN-NEXT: v_madak_f32 v0, 0, v0, 0x41c00000
|
|
; GCN-NEXT: v_rcp_f32_e32 v0, v0
|
|
; GCN-NEXT: s_movk_i32 s2, 0xffe8
|
|
; GCN-NEXT: v_mov_b32_e32 v8, 0
|
|
; GCN-NEXT: v_mov_b32_e32 v7, 0
|
|
; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
|
|
; GCN-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
|
|
; GCN-NEXT: v_trunc_f32_e32 v1, v1
|
|
; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
|
|
; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
|
|
; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
|
|
; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
|
|
; GCN-NEXT: s_mov_b32 s11, 0xf000
|
|
; GCN-NEXT: v_mul_hi_u32 v2, v0, s2
|
|
; GCN-NEXT: v_mul_lo_u32 v3, v1, s2
|
|
; GCN-NEXT: v_mul_lo_u32 v4, v0, s2
|
|
; GCN-NEXT: s_mov_b32 s10, -1
|
|
; GCN-NEXT: v_subrev_i32_e32 v2, vcc, v0, v2
|
|
; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
|
|
; GCN-NEXT: v_mul_lo_u32 v5, v0, v2
|
|
; GCN-NEXT: v_mul_hi_u32 v6, v0, v4
|
|
; GCN-NEXT: v_mul_hi_u32 v3, v0, v2
|
|
; GCN-NEXT: v_mul_hi_u32 v9, v1, v2
|
|
; GCN-NEXT: v_mul_lo_u32 v2, v1, v2
|
|
; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5
|
|
; GCN-NEXT: v_mul_lo_u32 v6, v1, v4
|
|
; GCN-NEXT: v_mul_hi_u32 v4, v1, v4
|
|
; GCN-NEXT: v_addc_u32_e32 v3, vcc, v8, v3, vcc
|
|
; GCN-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GCN-NEXT: s_mov_b32 s8, s4
|
|
; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v6
|
|
; GCN-NEXT: v_addc_u32_e32 v3, vcc, v3, v4, vcc
|
|
; GCN-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc
|
|
; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
|
|
; GCN-NEXT: v_add_i32_e64 v0, s[0:1], v0, v2
|
|
; GCN-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc
|
|
; GCN-NEXT: v_mul_hi_u32 v4, v0, s2
|
|
; GCN-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[0:1]
|
|
; GCN-NEXT: v_mul_lo_u32 v5, v2, s2
|
|
; GCN-NEXT: v_mul_lo_u32 v6, v0, s2
|
|
; GCN-NEXT: v_subrev_i32_e32 v4, vcc, v0, v4
|
|
; GCN-NEXT: s_mov_b32 s9, s5
|
|
; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v5
|
|
; GCN-NEXT: v_mul_lo_u32 v5, v0, v4
|
|
; GCN-NEXT: v_mul_hi_u32 v9, v0, v6
|
|
; GCN-NEXT: v_mul_hi_u32 v10, v0, v4
|
|
; GCN-NEXT: v_mul_hi_u32 v11, v2, v4
|
|
; GCN-NEXT: v_add_i32_e32 v5, vcc, v9, v5
|
|
; GCN-NEXT: v_addc_u32_e32 v9, vcc, v8, v10, vcc
|
|
; GCN-NEXT: v_mul_lo_u32 v10, v2, v6
|
|
; GCN-NEXT: v_mul_hi_u32 v6, v2, v6
|
|
; GCN-NEXT: v_mul_lo_u32 v2, v2, v4
|
|
; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v10
|
|
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v6, vcc
|
|
; GCN-NEXT: v_addc_u32_e32 v4, vcc, v11, v7, vcc
|
|
; GCN-NEXT: v_add_i32_e32 v2, vcc, v5, v2
|
|
; GCN-NEXT: v_addc_u32_e32 v4, vcc, v8, v4, vcc
|
|
; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v3
|
|
; GCN-NEXT: v_addc_u32_e64 v1, vcc, v1, v4, s[0:1]
|
|
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
|
|
; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GCN-NEXT: v_mul_lo_u32 v2, s6, v1
|
|
; GCN-NEXT: v_mul_hi_u32 v3, s6, v0
|
|
; GCN-NEXT: v_mul_hi_u32 v4, s6, v1
|
|
; GCN-NEXT: v_mul_hi_u32 v5, s7, v1
|
|
; GCN-NEXT: v_mul_lo_u32 v1, s7, v1
|
|
; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
|
|
; GCN-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc
|
|
; GCN-NEXT: v_mul_lo_u32 v4, s7, v0
|
|
; GCN-NEXT: v_mul_hi_u32 v0, s7, v0
|
|
; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4
|
|
; GCN-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc
|
|
; GCN-NEXT: v_addc_u32_e32 v2, vcc, v5, v7, vcc
|
|
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1
|
|
; GCN-NEXT: v_addc_u32_e32 v1, vcc, v8, v2, vcc
|
|
; GCN-NEXT: v_mul_hi_u32 v2, v0, 24
|
|
; GCN-NEXT: v_mul_lo_u32 v1, v1, 24
|
|
; GCN-NEXT: v_mul_lo_u32 v0, v0, 24
|
|
; GCN-NEXT: v_add_i32_e32 v1, vcc, v2, v1
|
|
; GCN-NEXT: v_sub_i32_e32 v0, vcc, s6, v0
|
|
; GCN-NEXT: v_mov_b32_e32 v2, s7
|
|
; GCN-NEXT: v_subb_u32_e32 v1, vcc, v2, v1, vcc
|
|
; GCN-NEXT: v_subrev_i32_e32 v2, vcc, 24, v0
|
|
; GCN-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v1, vcc
|
|
; GCN-NEXT: v_subrev_i32_e32 v4, vcc, 24, v2
|
|
; GCN-NEXT: v_subbrev_u32_e32 v5, vcc, 0, v3, vcc
|
|
; GCN-NEXT: v_cmp_lt_u32_e32 vcc, 23, v2
|
|
; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
|
|
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
|
|
; GCN-NEXT: v_cndmask_b32_e32 v6, -1, v6, vcc
|
|
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
|
|
; GCN-NEXT: v_cmp_lt_u32_e64 s[0:1], 23, v0
|
|
; GCN-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
|
|
; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1]
|
|
; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v1
|
|
; GCN-NEXT: v_cndmask_b32_e64 v5, -1, v5, s[0:1]
|
|
; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v5
|
|
; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
|
|
; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1]
|
|
; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
|
|
; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0
|
|
; GCN-NEXT: s_endpgm
|
|
;
|
|
; GCN-IR-LABEL: s_test_urem_k_den_i64:
|
|
; GCN-IR: ; %bb.0: ; %_udiv-special-cases
|
|
; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
|
|
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GCN-IR-NEXT: s_flbit_i32_b32 s2, s6
|
|
; GCN-IR-NEXT: s_flbit_i32_b32 s3, s7
|
|
; GCN-IR-NEXT: s_add_i32 s2, s2, 32
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v0, s3
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v1, s2
|
|
; GCN-IR-NEXT: v_cmp_eq_u32_e64 vcc, s7, 0
|
|
; GCN-IR-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc
|
|
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 59, v2
|
|
; GCN-IR-NEXT: v_subb_u32_e64 v1, s[2:3], 0, 0, vcc
|
|
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[0:1], s[6:7], 0
|
|
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[0:1]
|
|
; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], vcc
|
|
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[0:1]
|
|
; GCN-IR-NEXT: s_xor_b64 s[2:3], s[0:1], -1
|
|
; GCN-IR-NEXT: s_and_b64 s[2:3], s[2:3], vcc
|
|
; GCN-IR-NEXT: s_and_b64 vcc, exec, s[2:3]
|
|
; GCN-IR-NEXT: s_cbranch_vccz BB7_4
|
|
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
|
|
; GCN-IR-NEXT: v_add_i32_e32 v3, vcc, 1, v0
|
|
; GCN-IR-NEXT: v_addc_u32_e32 v4, vcc, 0, v1, vcc
|
|
; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[0:1], v[3:4], v[0:1]
|
|
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 63, v0
|
|
; GCN-IR-NEXT: v_lshl_b64 v[0:1], s[6:7], v0
|
|
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[0:1]
|
|
; GCN-IR-NEXT: s_cbranch_vccz BB7_5
|
|
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
|
|
; GCN-IR-NEXT: v_lshr_b64 v[6:7], s[6:7], v3
|
|
; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 0xffffffc4, v2
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v8, 0
|
|
; GCN-IR-NEXT: v_addc_u32_e64 v5, s[0:1], 0, -1, vcc
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v9, 0
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v3, 0
|
|
; GCN-IR-NEXT: BB7_3: ; %udiv-do-while
|
|
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
|
|
; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[6:7], 1
|
|
; GCN-IR-NEXT: v_lshrrev_b32_e32 v2, 31, v1
|
|
; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v2
|
|
; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
|
|
; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, 23, v6
|
|
; GCN-IR-NEXT: v_subb_u32_e32 v2, vcc, 0, v7, vcc
|
|
; GCN-IR-NEXT: v_or_b32_e32 v0, v8, v0
|
|
; GCN-IR-NEXT: v_ashrrev_i32_e32 v8, 31, v2
|
|
; GCN-IR-NEXT: v_and_b32_e32 v10, 24, v8
|
|
; GCN-IR-NEXT: v_and_b32_e32 v2, 1, v8
|
|
; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v4
|
|
; GCN-IR-NEXT: v_or_b32_e32 v1, v9, v1
|
|
; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v5, vcc
|
|
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5]
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v4, v8
|
|
; GCN-IR-NEXT: v_sub_i32_e64 v6, s[0:1], v6, v10
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v5, v9
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v9, v3
|
|
; GCN-IR-NEXT: v_subbrev_u32_e64 v7, s[0:1], 0, v7, s[0:1]
|
|
; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v8, v2
|
|
; GCN-IR-NEXT: s_cbranch_vccz BB7_3
|
|
; GCN-IR-NEXT: s_branch BB7_6
|
|
; GCN-IR-NEXT: BB7_4:
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v0, s7
|
|
; GCN-IR-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[0:1]
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v0, s6
|
|
; GCN-IR-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[0:1]
|
|
; GCN-IR-NEXT: s_branch BB7_7
|
|
; GCN-IR-NEXT: BB7_5:
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v2, 0
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v3, 0
|
|
; GCN-IR-NEXT: BB7_6: ; %Flow5
|
|
; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
|
|
; GCN-IR-NEXT: v_or_b32_e32 v0, v2, v0
|
|
; GCN-IR-NEXT: v_or_b32_e32 v1, v3, v1
|
|
; GCN-IR-NEXT: BB7_7: ; %udiv-end
|
|
; GCN-IR-NEXT: v_mul_hi_u32 v2, v0, 24
|
|
; GCN-IR-NEXT: v_mul_lo_u32 v1, v1, 24
|
|
; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, 24
|
|
; GCN-IR-NEXT: s_mov_b32 s3, 0xf000
|
|
; GCN-IR-NEXT: s_mov_b32 s2, -1
|
|
; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v2, v1
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v2, s7
|
|
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s6, v0
|
|
; GCN-IR-NEXT: s_mov_b32 s0, s4
|
|
; GCN-IR-NEXT: s_mov_b32 s1, s5
|
|
; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v2, v1, vcc
|
|
; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
|
|
; GCN-IR-NEXT: s_endpgm
|
|
%result = urem i64 %x, 24
|
|
store i64 %result, i64 addrspace(1)* %out
|
|
ret void
|
|
}
|
|
|
|
; FIXME: Constant bus violation
|
|
; define i64 @v_test_urem_k_num_i64(i64 %x) {
|
|
; %result = urem i64 24, %x
|
|
; ret i64 %result
|
|
; }
|
|
|
|
define i64 @v_test_urem_pow2_k_num_i64(i64 %x) {
|
|
; GCN-LABEL: v_test_urem_pow2_k_num_i64:
|
|
; GCN: ; %bb.0:
|
|
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GCN-NEXT: v_cvt_f32_u32_e32 v2, v0
|
|
; GCN-NEXT: v_cvt_f32_u32_e32 v3, v1
|
|
; GCN-NEXT: v_sub_i32_e32 v4, vcc, 0, v0
|
|
; GCN-NEXT: v_subb_u32_e32 v5, vcc, 0, v1, vcc
|
|
; GCN-NEXT: v_mov_b32_e32 v12, 0
|
|
; GCN-NEXT: v_mac_f32_e32 v2, 0x4f800000, v3
|
|
; GCN-NEXT: v_rcp_f32_e32 v2, v2
|
|
; GCN-NEXT: v_mov_b32_e32 v11, 0
|
|
; GCN-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2
|
|
; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2
|
|
; GCN-NEXT: v_trunc_f32_e32 v3, v3
|
|
; GCN-NEXT: v_mac_f32_e32 v2, 0xcf800000, v3
|
|
; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2
|
|
; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3
|
|
; GCN-NEXT: v_mul_hi_u32 v7, v4, v2
|
|
; GCN-NEXT: v_mul_lo_u32 v6, v4, v3
|
|
; GCN-NEXT: v_mul_lo_u32 v8, v5, v2
|
|
; GCN-NEXT: v_mul_lo_u32 v9, v4, v2
|
|
; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6
|
|
; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v8
|
|
; GCN-NEXT: v_mul_lo_u32 v8, v2, v6
|
|
; GCN-NEXT: v_mul_hi_u32 v10, v2, v9
|
|
; GCN-NEXT: v_mul_hi_u32 v7, v2, v6
|
|
; GCN-NEXT: v_mul_hi_u32 v13, v3, v6
|
|
; GCN-NEXT: v_mul_lo_u32 v6, v3, v6
|
|
; GCN-NEXT: v_add_i32_e32 v8, vcc, v10, v8
|
|
; GCN-NEXT: v_mul_lo_u32 v10, v3, v9
|
|
; GCN-NEXT: v_mul_hi_u32 v9, v3, v9
|
|
; GCN-NEXT: v_addc_u32_e32 v7, vcc, v12, v7, vcc
|
|
; GCN-NEXT: v_add_i32_e32 v8, vcc, v8, v10
|
|
; GCN-NEXT: v_addc_u32_e32 v7, vcc, v7, v9, vcc
|
|
; GCN-NEXT: v_addc_u32_e32 v8, vcc, v13, v11, vcc
|
|
; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6
|
|
; GCN-NEXT: v_add_i32_e64 v2, s[4:5], v2, v6
|
|
; GCN-NEXT: v_addc_u32_e32 v7, vcc, v12, v8, vcc
|
|
; GCN-NEXT: v_addc_u32_e64 v6, vcc, v3, v7, s[4:5]
|
|
; GCN-NEXT: v_mul_lo_u32 v8, v4, v6
|
|
; GCN-NEXT: v_mul_hi_u32 v9, v4, v2
|
|
; GCN-NEXT: v_mul_lo_u32 v5, v5, v2
|
|
; GCN-NEXT: v_mul_lo_u32 v4, v4, v2
|
|
; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8
|
|
; GCN-NEXT: v_add_i32_e32 v5, vcc, v8, v5
|
|
; GCN-NEXT: v_mul_lo_u32 v10, v2, v5
|
|
; GCN-NEXT: v_mul_hi_u32 v13, v2, v4
|
|
; GCN-NEXT: v_mul_hi_u32 v14, v2, v5
|
|
; GCN-NEXT: v_mul_hi_u32 v9, v6, v4
|
|
; GCN-NEXT: v_mul_lo_u32 v4, v6, v4
|
|
; GCN-NEXT: v_add_i32_e32 v10, vcc, v13, v10
|
|
; GCN-NEXT: v_mul_hi_u32 v8, v6, v5
|
|
; GCN-NEXT: v_addc_u32_e32 v13, vcc, v12, v14, vcc
|
|
; GCN-NEXT: v_mul_lo_u32 v5, v6, v5
|
|
; GCN-NEXT: v_add_i32_e32 v4, vcc, v10, v4
|
|
; GCN-NEXT: v_addc_u32_e32 v4, vcc, v13, v9, vcc
|
|
; GCN-NEXT: v_addc_u32_e32 v6, vcc, v8, v11, vcc
|
|
; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v5
|
|
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v12, v6, vcc
|
|
; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v7
|
|
; GCN-NEXT: v_addc_u32_e64 v3, vcc, v3, v5, s[4:5]
|
|
; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4
|
|
; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v3, vcc
|
|
; GCN-NEXT: v_lshrrev_b32_e32 v2, 17, v2
|
|
; GCN-NEXT: v_mul_lo_u32 v3, v1, v2
|
|
; GCN-NEXT: v_mul_hi_u32 v4, v0, v2
|
|
; GCN-NEXT: v_mul_lo_u32 v2, v0, v2
|
|
; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3
|
|
; GCN-NEXT: v_sub_i32_e32 v4, vcc, 0, v3
|
|
; GCN-NEXT: v_sub_i32_e32 v2, vcc, 0x8000, v2
|
|
; GCN-NEXT: v_subb_u32_e64 v4, s[4:5], v4, v1, vcc
|
|
; GCN-NEXT: v_sub_i32_e64 v5, s[4:5], v2, v0
|
|
; GCN-NEXT: v_subbrev_u32_e64 v6, s[6:7], 0, v4, s[4:5]
|
|
; GCN-NEXT: v_cmp_ge_u32_e64 s[6:7], v6, v1
|
|
; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[6:7]
|
|
; GCN-NEXT: v_cmp_ge_u32_e64 s[6:7], v5, v0
|
|
; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[6:7]
|
|
; GCN-NEXT: v_cmp_eq_u32_e64 s[6:7], v6, v1
|
|
; GCN-NEXT: v_subb_u32_e64 v4, s[4:5], v4, v1, s[4:5]
|
|
; GCN-NEXT: v_subb_u32_e32 v3, vcc, 0, v3, vcc
|
|
; GCN-NEXT: v_cndmask_b32_e64 v7, v7, v8, s[6:7]
|
|
; GCN-NEXT: v_sub_i32_e64 v8, s[4:5], v5, v0
|
|
; GCN-NEXT: v_subbrev_u32_e64 v4, s[4:5], 0, v4, s[4:5]
|
|
; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v3, v1
|
|
; GCN-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v7
|
|
; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
|
|
; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v2, v0
|
|
; GCN-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc
|
|
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v3, v1
|
|
; GCN-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc
|
|
; GCN-NEXT: v_cndmask_b32_e64 v5, v5, v8, s[4:5]
|
|
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
|
|
; GCN-NEXT: v_cndmask_b32_e64 v1, v6, v4, s[4:5]
|
|
; GCN-NEXT: v_cndmask_b32_e32 v0, v2, v5, vcc
|
|
; GCN-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
|
|
; GCN-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GCN-IR-LABEL: v_test_urem_pow2_k_num_i64:
|
|
; GCN-IR: ; %bb.0: ; %_udiv-special-cases
|
|
; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GCN-IR-NEXT: v_ffbh_u32_e32 v2, v0
|
|
; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, 32, v2
|
|
; GCN-IR-NEXT: v_ffbh_u32_e32 v3, v1
|
|
; GCN-IR-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
|
|
; GCN-IR-NEXT: v_cndmask_b32_e32 v8, v3, v2, vcc
|
|
; GCN-IR-NEXT: s_movk_i32 s6, 0xffd0
|
|
; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, s6, v8
|
|
; GCN-IR-NEXT: v_addc_u32_e64 v3, s[6:7], 0, -1, vcc
|
|
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
|
|
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[2:3]
|
|
; GCN-IR-NEXT: s_mov_b32 s8, 0x8000
|
|
; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], vcc
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v4, s8
|
|
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[2:3]
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v9, 0
|
|
; GCN-IR-NEXT: v_cndmask_b32_e64 v4, v4, 0, s[4:5]
|
|
; GCN-IR-NEXT: s_xor_b64 s[4:5], s[4:5], -1
|
|
; GCN-IR-NEXT: s_mov_b32 s9, 0
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v5, v9
|
|
; GCN-IR-NEXT: s_and_b64 s[4:5], s[4:5], vcc
|
|
; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
|
|
; GCN-IR-NEXT: s_cbranch_execz BB8_6
|
|
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
|
|
; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, 1, v2
|
|
; GCN-IR-NEXT: v_addc_u32_e32 v7, vcc, 0, v3, vcc
|
|
; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[6:7], v[2:3]
|
|
; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v2
|
|
; GCN-IR-NEXT: v_lshl_b64 v[2:3], s[8:9], v2
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v4, 0
|
|
; GCN-IR-NEXT: s_mov_b64 s[8:9], 0
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
|
|
; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; GCN-IR-NEXT: s_xor_b64 s[10:11], exec, s[4:5]
|
|
; GCN-IR-NEXT: s_cbranch_execz BB8_5
|
|
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
|
|
; GCN-IR-NEXT: s_mov_b32 s5, 0
|
|
; GCN-IR-NEXT: s_mov_b32 s4, 0x8000
|
|
; GCN-IR-NEXT: v_lshr_b64 v[10:11], s[4:5], v6
|
|
; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, -1, v0
|
|
; GCN-IR-NEXT: v_addc_u32_e32 v7, vcc, -1, v1, vcc
|
|
; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, 47, v8
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v12, 0
|
|
; GCN-IR-NEXT: v_subb_u32_e32 v9, vcc, 0, v9, vcc
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v13, 0
|
|
; GCN-IR-NEXT: BB8_3: ; %udiv-do-while
|
|
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
|
|
; GCN-IR-NEXT: v_lshl_b64 v[10:11], v[10:11], 1
|
|
; GCN-IR-NEXT: v_lshrrev_b32_e32 v4, 31, v3
|
|
; GCN-IR-NEXT: v_or_b32_e32 v10, v10, v4
|
|
; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
|
|
; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, v6, v10
|
|
; GCN-IR-NEXT: v_subb_u32_e32 v4, vcc, v7, v11, vcc
|
|
; GCN-IR-NEXT: v_or_b32_e32 v2, v12, v2
|
|
; GCN-IR-NEXT: v_ashrrev_i32_e32 v12, 31, v4
|
|
; GCN-IR-NEXT: v_and_b32_e32 v15, v12, v0
|
|
; GCN-IR-NEXT: v_and_b32_e32 v4, 1, v12
|
|
; GCN-IR-NEXT: v_and_b32_e32 v14, v12, v1
|
|
; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, 1, v8
|
|
; GCN-IR-NEXT: v_or_b32_e32 v3, v13, v3
|
|
; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, 0, v9, vcc
|
|
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[12:13], v[8:9]
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v8, v12
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
|
|
; GCN-IR-NEXT: v_sub_i32_e64 v10, s[4:5], v10, v15
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v9, v13
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v13, v5
|
|
; GCN-IR-NEXT: v_subb_u32_e64 v11, s[4:5], v11, v14, s[4:5]
|
|
; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9]
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v12, v4
|
|
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9]
|
|
; GCN-IR-NEXT: s_cbranch_execnz BB8_3
|
|
; GCN-IR-NEXT: ; %bb.4: ; %Flow
|
|
; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
|
|
; GCN-IR-NEXT: BB8_5: ; %Flow3
|
|
; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
|
|
; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
|
|
; GCN-IR-NEXT: v_or_b32_e32 v5, v5, v3
|
|
; GCN-IR-NEXT: v_or_b32_e32 v4, v4, v2
|
|
; GCN-IR-NEXT: BB8_6: ; %Flow4
|
|
; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]
|
|
; GCN-IR-NEXT: v_mul_lo_u32 v2, v0, v5
|
|
; GCN-IR-NEXT: v_mul_hi_u32 v3, v0, v4
|
|
; GCN-IR-NEXT: v_mul_lo_u32 v1, v1, v4
|
|
; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, v4
|
|
; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, v3, v2
|
|
; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v2, v1
|
|
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 0x8000, v0
|
|
; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GCN-IR-NEXT: s_setpc_b64 s[30:31]
|
|
%result = urem i64 32768, %x
|
|
ret i64 %result
|
|
}
|
|
|
|
define i64 @v_test_urem_pow2_k_den_i64(i64 %x) {
|
|
; GCN-LABEL: v_test_urem_pow2_k_den_i64:
|
|
; GCN: ; %bb.0:
|
|
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GCN-NEXT: v_and_b32_e32 v0, 0x7fff, v0
|
|
; GCN-NEXT: v_mov_b32_e32 v1, 0
|
|
; GCN-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GCN-IR-LABEL: v_test_urem_pow2_k_den_i64:
|
|
; GCN-IR: ; %bb.0: ; %_udiv-special-cases
|
|
; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GCN-IR-NEXT: v_ffbh_u32_e32 v2, v0
|
|
; GCN-IR-NEXT: v_add_i32_e64 v2, s[4:5], 32, v2
|
|
; GCN-IR-NEXT: v_ffbh_u32_e32 v3, v1
|
|
; GCN-IR-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v1
|
|
; GCN-IR-NEXT: v_cndmask_b32_e64 v6, v3, v2, s[4:5]
|
|
; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 48, v6
|
|
; GCN-IR-NEXT: v_subb_u32_e64 v3, s[4:5], 0, 0, s[4:5]
|
|
; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]
|
|
; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[4:5], 63, v[2:3]
|
|
; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
|
|
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[2:3]
|
|
; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1
|
|
; GCN-IR-NEXT: v_cndmask_b32_e64 v5, v1, 0, s[4:5]
|
|
; GCN-IR-NEXT: v_cndmask_b32_e64 v4, v0, 0, s[4:5]
|
|
; GCN-IR-NEXT: s_and_b64 s[4:5], s[6:7], vcc
|
|
; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
|
|
; GCN-IR-NEXT: s_cbranch_execz BB9_6
|
|
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
|
|
; GCN-IR-NEXT: v_add_i32_e32 v7, vcc, 1, v2
|
|
; GCN-IR-NEXT: v_addc_u32_e32 v8, vcc, 0, v3, vcc
|
|
; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[7:8], v[2:3]
|
|
; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v2
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v4, 0
|
|
; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[0:1], v2
|
|
; GCN-IR-NEXT: s_mov_b64 s[8:9], 0
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
|
|
; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; GCN-IR-NEXT: s_xor_b64 s[10:11], exec, s[4:5]
|
|
; GCN-IR-NEXT: s_cbranch_execz BB9_5
|
|
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v10, 0
|
|
; GCN-IR-NEXT: v_lshr_b64 v[8:9], v[0:1], v7
|
|
; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, 0xffffffcf, v6
|
|
; GCN-IR-NEXT: v_addc_u32_e64 v7, s[4:5], 0, -1, vcc
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v11, 0
|
|
; GCN-IR-NEXT: s_movk_i32 s12, 0x7fff
|
|
; GCN-IR-NEXT: BB9_3: ; %udiv-do-while
|
|
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
|
|
; GCN-IR-NEXT: v_lshl_b64 v[8:9], v[8:9], 1
|
|
; GCN-IR-NEXT: v_lshrrev_b32_e32 v4, 31, v3
|
|
; GCN-IR-NEXT: v_or_b32_e32 v8, v8, v4
|
|
; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
|
|
; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, s12, v8
|
|
; GCN-IR-NEXT: v_subb_u32_e32 v4, vcc, 0, v9, vcc
|
|
; GCN-IR-NEXT: v_or_b32_e32 v2, v10, v2
|
|
; GCN-IR-NEXT: v_ashrrev_i32_e32 v10, 31, v4
|
|
; GCN-IR-NEXT: v_and_b32_e32 v13, 0x8000, v10
|
|
; GCN-IR-NEXT: v_and_b32_e32 v4, 1, v10
|
|
; GCN-IR-NEXT: v_add_i32_e32 v10, vcc, 1, v6
|
|
; GCN-IR-NEXT: v_or_b32_e32 v3, v11, v3
|
|
; GCN-IR-NEXT: v_addc_u32_e32 v11, vcc, 0, v7, vcc
|
|
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[10:11], v[6:7]
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v6, v10
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v7, v11
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v11, v5
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v12, 0
|
|
; GCN-IR-NEXT: v_sub_i32_e64 v8, s[4:5], v8, v13
|
|
; GCN-IR-NEXT: v_subb_u32_e64 v9, s[4:5], v9, v12, s[4:5]
|
|
; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9]
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v10, v4
|
|
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9]
|
|
; GCN-IR-NEXT: s_cbranch_execnz BB9_3
|
|
; GCN-IR-NEXT: ; %bb.4: ; %Flow
|
|
; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
|
|
; GCN-IR-NEXT: BB9_5: ; %Flow3
|
|
; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
|
|
; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
|
|
; GCN-IR-NEXT: v_or_b32_e32 v5, v5, v3
|
|
; GCN-IR-NEXT: v_or_b32_e32 v4, v4, v2
|
|
; GCN-IR-NEXT: BB9_6: ; %Flow4
|
|
; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]
|
|
; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[4:5], 15
|
|
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
|
|
; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc
|
|
; GCN-IR-NEXT: s_setpc_b64 s[30:31]
|
|
%result = urem i64 %x, 32768
|
|
ret i64 %result
|
|
}
|
|
|
|
define amdgpu_kernel void @s_test_urem24_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
|
|
; GCN-LABEL: s_test_urem24_k_num_i64:
|
|
; GCN: ; %bb.0:
|
|
; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
|
|
; GCN-NEXT: s_mov_b32 s5, 0x41c00000
|
|
; GCN-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GCN-NEXT: s_mov_b32 s2, -1
|
|
; GCN-NEXT: s_lshr_b32 s4, s3, 8
|
|
; GCN-NEXT: v_cvt_f32_u32_e32 v0, s4
|
|
; GCN-NEXT: s_mov_b32 s3, 0xf000
|
|
; GCN-NEXT: v_rcp_iflag_f32_e32 v1, v0
|
|
; GCN-NEXT: v_mul_f32_e32 v1, s5, v1
|
|
; GCN-NEXT: v_trunc_f32_e32 v1, v1
|
|
; GCN-NEXT: v_cvt_u32_f32_e32 v2, v1
|
|
; GCN-NEXT: v_mad_f32 v1, -v1, v0, s5
|
|
; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
|
|
; GCN-NEXT: v_mov_b32_e32 v1, 0
|
|
; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc
|
|
; GCN-NEXT: v_mul_lo_u32 v0, v0, s4
|
|
; GCN-NEXT: v_sub_i32_e32 v0, vcc, 24, v0
|
|
; GCN-NEXT: v_and_b32_e32 v0, 0xffffff, v0
|
|
; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
|
|
; GCN-NEXT: s_endpgm
|
|
;
|
|
; GCN-IR-LABEL: s_test_urem24_k_num_i64:
|
|
; GCN-IR: ; %bb.0:
|
|
; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
|
|
; GCN-IR-NEXT: s_mov_b32 s5, 0x41c00000
|
|
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GCN-IR-NEXT: s_mov_b32 s2, -1
|
|
; GCN-IR-NEXT: s_lshr_b32 s4, s3, 8
|
|
; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s4
|
|
; GCN-IR-NEXT: s_mov_b32 s3, 0xf000
|
|
; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v1, v0
|
|
; GCN-IR-NEXT: v_mul_f32_e32 v1, s5, v1
|
|
; GCN-IR-NEXT: v_trunc_f32_e32 v1, v1
|
|
; GCN-IR-NEXT: v_cvt_u32_f32_e32 v2, v1
|
|
; GCN-IR-NEXT: v_mad_f32 v1, -v1, v0, s5
|
|
; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v1, 0
|
|
; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc
|
|
; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s4
|
|
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 24, v0
|
|
; GCN-IR-NEXT: v_and_b32_e32 v0, 0xffffff, v0
|
|
; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
|
|
; GCN-IR-NEXT: s_endpgm
|
|
%x.shr = lshr i64 %x, 40
|
|
%result = urem i64 24, %x.shr
|
|
store i64 %result, i64 addrspace(1)* %out
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @s_test_urem24_k_den_i64(i64 addrspace(1)* %out, i64 %x) {
|
|
; GCN-LABEL: s_test_urem24_k_den_i64:
|
|
; GCN: ; %bb.0:
|
|
; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
|
|
; GCN-NEXT: s_mov_b32 s4, 0x46b6fe00
|
|
; GCN-NEXT: s_mov_b32 s7, 0xf000
|
|
; GCN-NEXT: s_mov_b32 s6, -1
|
|
; GCN-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GCN-NEXT: s_lshr_b32 s2, s3, 8
|
|
; GCN-NEXT: v_cvt_f32_u32_e32 v0, s2
|
|
; GCN-NEXT: s_movk_i32 s3, 0x5b7f
|
|
; GCN-NEXT: s_mov_b32 s5, s1
|
|
; GCN-NEXT: v_mul_f32_e32 v1, 0x38331158, v0
|
|
; GCN-NEXT: v_trunc_f32_e32 v1, v1
|
|
; GCN-NEXT: v_cvt_u32_f32_e32 v2, v1
|
|
; GCN-NEXT: v_mad_f32 v0, -v1, s4, v0
|
|
; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, s4
|
|
; GCN-NEXT: s_mov_b32 s4, s0
|
|
; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc
|
|
; GCN-NEXT: v_mul_lo_u32 v0, v0, s3
|
|
; GCN-NEXT: v_mov_b32_e32 v1, 0
|
|
; GCN-NEXT: v_sub_i32_e32 v0, vcc, s2, v0
|
|
; GCN-NEXT: v_and_b32_e32 v0, 0xffffff, v0
|
|
; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
|
|
; GCN-NEXT: s_endpgm
|
|
;
|
|
; GCN-IR-LABEL: s_test_urem24_k_den_i64:
|
|
; GCN-IR: ; %bb.0:
|
|
; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
|
|
; GCN-IR-NEXT: s_mov_b32 s4, 0x46b6fe00
|
|
; GCN-IR-NEXT: s_mov_b32 s7, 0xf000
|
|
; GCN-IR-NEXT: s_mov_b32 s6, -1
|
|
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GCN-IR-NEXT: s_lshr_b32 s2, s3, 8
|
|
; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s2
|
|
; GCN-IR-NEXT: s_movk_i32 s3, 0x5b7f
|
|
; GCN-IR-NEXT: s_mov_b32 s5, s1
|
|
; GCN-IR-NEXT: v_mul_f32_e32 v1, 0x38331158, v0
|
|
; GCN-IR-NEXT: v_trunc_f32_e32 v1, v1
|
|
; GCN-IR-NEXT: v_cvt_u32_f32_e32 v2, v1
|
|
; GCN-IR-NEXT: v_mad_f32 v0, -v1, s4, v0
|
|
; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, s4
|
|
; GCN-IR-NEXT: s_mov_b32 s4, s0
|
|
; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc
|
|
; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s3
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v1, 0
|
|
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s2, v0
|
|
; GCN-IR-NEXT: v_and_b32_e32 v0, 0xffffff, v0
|
|
; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
|
|
; GCN-IR-NEXT: s_endpgm
|
|
%x.shr = lshr i64 %x, 40
|
|
%result = urem i64 %x.shr, 23423
|
|
store i64 %result, i64 addrspace(1)* %out
|
|
ret void
|
|
}
|
|
|
|
define i64 @v_test_urem24_k_num_i64(i64 %x) {
|
|
; GCN-LABEL: v_test_urem24_k_num_i64:
|
|
; GCN: ; %bb.0:
|
|
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GCN-NEXT: v_lshrrev_b32_e32 v0, 8, v1
|
|
; GCN-NEXT: v_cvt_f32_u32_e32 v1, v0
|
|
; GCN-NEXT: s_mov_b32 s4, 0x41c00000
|
|
; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v1
|
|
; GCN-NEXT: v_mul_f32_e32 v2, s4, v2
|
|
; GCN-NEXT: v_trunc_f32_e32 v2, v2
|
|
; GCN-NEXT: v_cvt_u32_f32_e32 v3, v2
|
|
; GCN-NEXT: v_mad_f32 v2, -v2, v1, s4
|
|
; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v1
|
|
; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc
|
|
; GCN-NEXT: v_mul_lo_u32 v0, v1, v0
|
|
; GCN-NEXT: v_mov_b32_e32 v1, 0
|
|
; GCN-NEXT: v_sub_i32_e32 v0, vcc, 24, v0
|
|
; GCN-NEXT: v_and_b32_e32 v0, 0xffffff, v0
|
|
; GCN-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GCN-IR-LABEL: v_test_urem24_k_num_i64:
|
|
; GCN-IR: ; %bb.0:
|
|
; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GCN-IR-NEXT: v_lshrrev_b32_e32 v0, 8, v1
|
|
; GCN-IR-NEXT: v_cvt_f32_u32_e32 v1, v0
|
|
; GCN-IR-NEXT: s_mov_b32 s4, 0x41c00000
|
|
; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v1
|
|
; GCN-IR-NEXT: v_mul_f32_e32 v2, s4, v2
|
|
; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2
|
|
; GCN-IR-NEXT: v_cvt_u32_f32_e32 v3, v2
|
|
; GCN-IR-NEXT: v_mad_f32 v2, -v2, v1, s4
|
|
; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v1
|
|
; GCN-IR-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc
|
|
; GCN-IR-NEXT: v_mul_lo_u32 v0, v1, v0
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v1, 0
|
|
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 24, v0
|
|
; GCN-IR-NEXT: v_and_b32_e32 v0, 0xffffff, v0
|
|
; GCN-IR-NEXT: s_setpc_b64 s[30:31]
|
|
%x.shr = lshr i64 %x, 40
|
|
%result = urem i64 24, %x.shr
|
|
ret i64 %result
|
|
}
|
|
|
|
define i64 @v_test_urem24_pow2_k_num_i64(i64 %x) {
|
|
; GCN-LABEL: v_test_urem24_pow2_k_num_i64:
|
|
; GCN: ; %bb.0:
|
|
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GCN-NEXT: v_lshrrev_b32_e32 v0, 8, v1
|
|
; GCN-NEXT: v_cvt_f32_u32_e32 v1, v0
|
|
; GCN-NEXT: s_mov_b32 s4, 0x47000000
|
|
; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v1
|
|
; GCN-NEXT: v_mul_f32_e32 v2, s4, v2
|
|
; GCN-NEXT: v_trunc_f32_e32 v2, v2
|
|
; GCN-NEXT: v_cvt_u32_f32_e32 v3, v2
|
|
; GCN-NEXT: v_mad_f32 v2, -v2, v1, s4
|
|
; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v1
|
|
; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc
|
|
; GCN-NEXT: v_mul_lo_u32 v0, v1, v0
|
|
; GCN-NEXT: v_mov_b32_e32 v1, 0
|
|
; GCN-NEXT: v_sub_i32_e32 v0, vcc, 0x8000, v0
|
|
; GCN-NEXT: v_and_b32_e32 v0, 0xffffff, v0
|
|
; GCN-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GCN-IR-LABEL: v_test_urem24_pow2_k_num_i64:
|
|
; GCN-IR: ; %bb.0:
|
|
; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GCN-IR-NEXT: v_lshrrev_b32_e32 v0, 8, v1
|
|
; GCN-IR-NEXT: v_cvt_f32_u32_e32 v1, v0
|
|
; GCN-IR-NEXT: s_mov_b32 s4, 0x47000000
|
|
; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v1
|
|
; GCN-IR-NEXT: v_mul_f32_e32 v2, s4, v2
|
|
; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2
|
|
; GCN-IR-NEXT: v_cvt_u32_f32_e32 v3, v2
|
|
; GCN-IR-NEXT: v_mad_f32 v2, -v2, v1, s4
|
|
; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v1
|
|
; GCN-IR-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc
|
|
; GCN-IR-NEXT: v_mul_lo_u32 v0, v1, v0
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v1, 0
|
|
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 0x8000, v0
|
|
; GCN-IR-NEXT: v_and_b32_e32 v0, 0xffffff, v0
|
|
; GCN-IR-NEXT: s_setpc_b64 s[30:31]
|
|
%x.shr = lshr i64 %x, 40
|
|
%result = urem i64 32768, %x.shr
|
|
ret i64 %result
|
|
}
|
|
|
|
define i64 @v_test_urem24_pow2_k_den_i64(i64 %x) {
|
|
; GCN-LABEL: v_test_urem24_pow2_k_den_i64:
|
|
; GCN: ; %bb.0:
|
|
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GCN-NEXT: v_bfe_u32 v0, v1, 8, 15
|
|
; GCN-NEXT: v_mov_b32_e32 v1, 0
|
|
; GCN-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GCN-IR-LABEL: v_test_urem24_pow2_k_den_i64:
|
|
; GCN-IR: ; %bb.0:
|
|
; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GCN-IR-NEXT: v_lshrrev_b32_e32 v0, 8, v1
|
|
; GCN-IR-NEXT: v_cvt_f32_u32_e32 v1, v0
|
|
; GCN-IR-NEXT: s_mov_b32 s4, 0x47000000
|
|
; GCN-IR-NEXT: v_mul_f32_e32 v2, 0x38000000, v1
|
|
; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2
|
|
; GCN-IR-NEXT: v_cvt_u32_f32_e32 v3, v2
|
|
; GCN-IR-NEXT: v_mad_f32 v1, -v2, s4, v1
|
|
; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, s4
|
|
; GCN-IR-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc
|
|
; GCN-IR-NEXT: v_lshlrev_b32_e32 v1, 15, v1
|
|
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
|
|
; GCN-IR-NEXT: v_and_b32_e32 v0, 0xffffff, v0
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v1, 0
|
|
; GCN-IR-NEXT: s_setpc_b64 s[30:31]
|
|
%x.shr = lshr i64 %x, 40
|
|
%result = urem i64 %x.shr, 32768
|
|
ret i64 %result
|
|
}
|