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llvm-mirror/test/CodeGen/PowerPC/select-addrRegRegOnly.ll
Jinsong Ji c7cbe2ad6b [PowerPC] Support extended mnemonics mffprwz etc.
Summary:
Reported in https://github.com/opencv/opencv/issues/15413.

We have serveral extended mnemonics for Move To/From Vector-Scalar Register Instructions
eg: mffprd,mtfprd etc.

We only support one of them, this patch add the others.

Reviewers: nemanjai, steven.zhang, hfinkel, #powerpc

Reviewed By: hfinkel

Subscribers: wuzish, qcolombet, hiraditya, kbarton, MaskRay, shchenz, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D66963

llvm-svn: 370411
2019-08-29 21:53:59 +00:00

38 lines
1.3 KiB
LLVM

; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mcpu=pwr8 -mtriple=powerpc64-unknown-unknown -verify-machineinstrs < %s | FileCheck %s
; Function Attrs: norecurse nounwind readonly
define float @testSingleAccess(i32* nocapture readonly %arr) local_unnamed_addr #0 {
; CHECK-LABEL: testSingleAccess:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi 3, 3, 8
; CHECK-NEXT: lfiwax 0, 0, 3
; CHECK-NEXT: xscvsxdsp 1, 0
; CHECK-NEXT: blr
entry:
%arrayidx = getelementptr inbounds i32, i32* %arr, i64 2
%0 = load i32, i32* %arrayidx, align 4
%conv = sitofp i32 %0 to float
ret float %conv
}
; Function Attrs: norecurse nounwind readonly
define float @testMultipleAccess(i32* nocapture readonly %arr) local_unnamed_addr #0 {
; CHECK-LABEL: testMultipleAccess:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lwz 4, 8(3)
; CHECK-NEXT: lwz 3, 12(3)
; CHECK-NEXT: add 3, 3, 4
; CHECK-NEXT: mtfprwa 0, 3
; CHECK-NEXT: xscvsxdsp 1, 0
; CHECK-NEXT: blr
entry:
%arrayidx = getelementptr inbounds i32, i32* %arr, i64 2
%0 = load i32, i32* %arrayidx, align 4
%arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 3
%1 = load i32, i32* %arrayidx1, align 4
%add = add nsw i32 %1, %0
%conv = sitofp i32 %add to float
ret float %conv
}