Rafael Auler 89b73ed5fd [X86][3DNOW] Teach decoder about AMD 3DNow! instrs ... Summary: This patch makes the decoder understand old AMD 3DNow! instructions that have never been properly supported in the X86 disassembler, despite being supported in other subsystems. Hopefully this should make the X86 decoder more complete with respect to binaries containing legacy code. Reviewers: craig.topper Reviewed By: craig.topper Subscribers: llvm-commits, maksfb, bruno Differential Revision: https://reviews.llvm.org/D43311 llvm-svn: 325295		2018-02-15 21:20:31 +00:00
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AArch64	[AArch64][SVE] Asm: Add AND_ZI instructions and aliases	2018-02-06 13:13:21 +00:00
AMDGPU	[AMDGPU][MC] Corrected dst/data size for MIMG opcodes with d16 modifier	2018-02-05 14:18:53 +00:00
ARM	[ARM] Don't print "Requires NEON" error message for M-profile	2018-02-13 11:46:38 +00:00
AsmParser	Store defined macros in MCContext.	2018-02-14 16:34:27 +00:00
AVR
BPF
COFF	[CodeView] Add line numbers for inlined call sites	2018-01-18 22:55:43 +00:00
Disassembler	[X86][3DNOW] Teach decoder about AMD 3DNow! instrs	2018-02-15 21:20:31 +00:00
ELF	[DWARFv5] Fix dumper to show the file table starts at index 0.	2018-02-08 23:08:02 +00:00
Hexagon	[Hexagon] Express calling conventions via .td file instead of hand-coding	2018-02-09 15:30:02 +00:00
Lanai
MachO	Fix regex from r324279 more better.	2018-02-06 00:43:26 +00:00
Markup
Mips	Make test changes added in r324584 more robust by using a regex instead of hard coded MCInst numbers.	2018-02-09 02:13:15 +00:00
PowerPC	[PowerPC, AsmParser] Enable the mnemonic spell corrector	2017-12-16 02:42:18 +00:00
RISCV	[RISCV] Add support for %pcrel_lo.	2018-02-06 00:55:23 +00:00
Sparc
SystemZ
WebAssembly	[WebAssembly] Add mechanisms for specifying an explicit import module name.	2018-02-09 23:13:22 +00:00
X86	[X86] Change 32 and 64 bit versions of LSL instruction have a 16-bit memory operand.	2018-02-15 01:21:53 +00:00