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d4c615be8c
Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
21 lines
672 B
LLVM
21 lines
672 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mcpu=zEC12 -o - %s | FileCheck %s
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target triple = "s390x-ibm-linux"
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define <2 x float> @pr32505(<2 x i8> * %a) {
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; CHECK-LABEL: pr32505:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lbh %r0, 1(%r2)
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; CHECK-NEXT: lbh %r1, 0(%r2)
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; CHECK-NEXT: ldgr %f0, %r1
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; CHECK-NEXT: ldgr %f2, %r0
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; CHECK-NEXT: # kill: def $f0s killed $f0s killed $f0d
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; CHECK-NEXT: # kill: def $f2s killed $f2s killed $f2d
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; CHECK-NEXT: br %r14
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%L17 = load <2 x i8>, <2 x i8>* %a
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%Se21 = sext <2 x i8> %L17 to <2 x i32>
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%BC = bitcast <2 x i32> %Se21 to <2 x float>
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ret <2 x float> %BC
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}
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