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3299 lines
112 KiB
TableGen
3299 lines
112 KiB
TableGen
//=- HexagonInstrInfoV4.td - Target Desc. for Hexagon Target -*- tablegen -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the Hexagon V4 instructions in TableGen format.
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//
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//===----------------------------------------------------------------------===//
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def DuplexIClass0: InstDuplex < 0 >;
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def DuplexIClass1: InstDuplex < 1 >;
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def DuplexIClass2: InstDuplex < 2 >;
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let isExtendable = 1 in {
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def DuplexIClass3: InstDuplex < 3 >;
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def DuplexIClass4: InstDuplex < 4 >;
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def DuplexIClass5: InstDuplex < 5 >;
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def DuplexIClass6: InstDuplex < 6 >;
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def DuplexIClass7: InstDuplex < 7 >;
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}
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def DuplexIClass8: InstDuplex < 8 >;
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def DuplexIClass9: InstDuplex < 9 >;
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def DuplexIClassA: InstDuplex < 0xA >;
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def DuplexIClassB: InstDuplex < 0xB >;
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def DuplexIClassC: InstDuplex < 0xC >;
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def DuplexIClassD: InstDuplex < 0xD >;
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def DuplexIClassE: InstDuplex < 0xE >;
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def DuplexIClassF: InstDuplex < 0xF >;
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let hasSideEffects = 0 in
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class T_Immext<Operand ImmType>
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: EXTENDERInst<(outs), (ins ImmType:$imm),
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"immext(#$imm)", []> {
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bits<32> imm;
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let IClass = 0b0000;
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let Inst{27-16} = imm{31-20};
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let Inst{13-0} = imm{19-6};
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}
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def A4_ext : T_Immext<u26_6Imm>;
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let isCodeGenOnly = 1 in {
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let isBranch = 1 in
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def A4_ext_b : T_Immext<brtarget>;
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let isCall = 1 in
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def A4_ext_c : T_Immext<calltarget>;
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def A4_ext_g : T_Immext<globaladdress>;
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}
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// Hexagon V4 Architecture spec defines 8 instruction classes:
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// LD ST ALU32 XTYPE J JR MEMOP NV CR SYSTEM(system is not implemented in the
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// compiler)
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// LD Instructions:
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// ========================================
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// Loads (8/16/32/64 bit)
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// Deallocframe
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// ST Instructions:
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// ========================================
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// Stores (8/16/32/64 bit)
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// Allocframe
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// ALU32 Instructions:
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// ========================================
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// Arithmetic / Logical (32 bit)
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// Vector Halfword
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// XTYPE Instructions (32/64 bit):
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// ========================================
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// Arithmetic, Logical, Bit Manipulation
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// Multiply (Integer, Fractional, Complex)
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// Permute / Vector Permute Operations
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// Predicate Operations
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// Shift / Shift with Add/Sub/Logical
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// Vector Byte ALU
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// Vector Halfword (ALU, Shift, Multiply)
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// Vector Word (ALU, Shift)
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// J Instructions:
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// ========================================
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// Jump/Call PC-relative
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// JR Instructions:
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// ========================================
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// Jump/Call Register
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// MEMOP Instructions:
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// ========================================
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// Operation on memory (8/16/32 bit)
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// NV Instructions:
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// ========================================
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// New-value Jumps
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// New-value Stores
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// CR Instructions:
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// ========================================
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// Control-Register Transfers
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// Hardware Loop Setup
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// Predicate Logicals & Reductions
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// SYSTEM Instructions (not implemented in the compiler):
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// ========================================
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// Prefetch
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// Cache Maintenance
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// Bus Operations
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//===----------------------------------------------------------------------===//
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// ALU32 +
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//===----------------------------------------------------------------------===//
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class T_ALU32_3op_not<string mnemonic, bits<3> MajOp, bits<3> MinOp,
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bit OpsRev>
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: T_ALU32_3op<mnemonic, MajOp, MinOp, OpsRev, 0> {
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let AsmString = "$Rd = "#mnemonic#"($Rs, ~$Rt)";
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}
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let BaseOpcode = "andn_rr", CextOpcode = "andn" in
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def A4_andn : T_ALU32_3op_not<"and", 0b001, 0b100, 1>;
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let BaseOpcode = "orn_rr", CextOpcode = "orn" in
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def A4_orn : T_ALU32_3op_not<"or", 0b001, 0b101, 1>;
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let CextOpcode = "rcmp.eq" in
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def A4_rcmpeq : T_ALU32_3op<"cmp.eq", 0b011, 0b010, 0, 1>;
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let CextOpcode = "!rcmp.eq" in
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def A4_rcmpneq : T_ALU32_3op<"!cmp.eq", 0b011, 0b011, 0, 1>;
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def C4_cmpneq : T_ALU32_3op_cmp<"!cmp.eq", 0b00, 1, 1>;
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def C4_cmplte : T_ALU32_3op_cmp<"!cmp.gt", 0b10, 1, 0>;
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def C4_cmplteu : T_ALU32_3op_cmp<"!cmp.gtu", 0b11, 1, 0>;
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class T_CMP_rrbh<string mnemonic, bits<3> MinOp, bit IsComm>
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: SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),
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"$Pd = "#mnemonic#"($Rs, $Rt)", [], "", S_3op_tc_2early_SLOT23>,
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ImmRegRel {
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let InputType = "reg";
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let CextOpcode = mnemonic;
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let isCompare = 1;
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let isCommutable = IsComm;
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let hasSideEffects = 0;
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bits<2> Pd;
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bits<5> Rs;
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bits<5> Rt;
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let IClass = 0b1100;
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let Inst{27-21} = 0b0111110;
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let Inst{20-16} = Rs;
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let Inst{12-8} = Rt;
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let Inst{7-5} = MinOp;
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let Inst{1-0} = Pd;
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}
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def A4_cmpbeq : T_CMP_rrbh<"cmpb.eq", 0b110, 1>;
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def A4_cmpbgt : T_CMP_rrbh<"cmpb.gt", 0b010, 0>;
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def A4_cmpbgtu : T_CMP_rrbh<"cmpb.gtu", 0b111, 0>;
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def A4_cmpheq : T_CMP_rrbh<"cmph.eq", 0b011, 1>;
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def A4_cmphgt : T_CMP_rrbh<"cmph.gt", 0b100, 0>;
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def A4_cmphgtu : T_CMP_rrbh<"cmph.gtu", 0b101, 0>;
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class T_CMP_ribh<string mnemonic, bits<2> MajOp, bit IsHalf, bit IsComm,
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Operand ImmType, bit IsImmExt, bit IsImmSigned, int ImmBits>
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: ALU64Inst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, ImmType:$Imm),
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"$Pd = "#mnemonic#"($Rs, #$Imm)", [], "", ALU64_tc_2early_SLOT23>,
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ImmRegRel {
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let InputType = "imm";
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let CextOpcode = mnemonic;
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let isCompare = 1;
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let isCommutable = IsComm;
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let hasSideEffects = 0;
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let isExtendable = IsImmExt;
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let opExtendable = !if (IsImmExt, 2, 0);
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let isExtentSigned = IsImmSigned;
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let opExtentBits = ImmBits;
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bits<2> Pd;
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bits<5> Rs;
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bits<8> Imm;
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let IClass = 0b1101;
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let Inst{27-24} = 0b1101;
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let Inst{22-21} = MajOp;
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let Inst{20-16} = Rs;
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let Inst{12-5} = Imm;
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let Inst{4} = 0b0;
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let Inst{3} = IsHalf;
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let Inst{1-0} = Pd;
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}
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def A4_cmpbeqi : T_CMP_ribh<"cmpb.eq", 0b00, 0, 1, u8_0Imm, 0, 0, 8>;
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def A4_cmpbgti : T_CMP_ribh<"cmpb.gt", 0b01, 0, 0, s8_0Imm, 0, 1, 8>;
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def A4_cmpbgtui : T_CMP_ribh<"cmpb.gtu", 0b10, 0, 0, u7_0Ext, 1, 0, 7>;
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def A4_cmpheqi : T_CMP_ribh<"cmph.eq", 0b00, 1, 1, s8_0Ext, 1, 1, 8>;
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def A4_cmphgti : T_CMP_ribh<"cmph.gt", 0b01, 1, 0, s8_0Ext, 1, 1, 8>;
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def A4_cmphgtui : T_CMP_ribh<"cmph.gtu", 0b10, 1, 0, u7_0Ext, 1, 0, 7>;
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class T_RCMP_EQ_ri<string mnemonic, bit IsNeg>
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: ALU32_ri<(outs IntRegs:$Rd), (ins IntRegs:$Rs, s8_0Ext:$s8),
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"$Rd = "#mnemonic#"($Rs, #$s8)", [], "", ALU32_2op_tc_1_SLOT0123>,
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ImmRegRel {
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let InputType = "imm";
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let CextOpcode = !if (IsNeg, "!rcmp.eq", "rcmp.eq");
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let isExtendable = 1;
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let opExtendable = 2;
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let isExtentSigned = 1;
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let opExtentBits = 8;
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let hasNewValue = 1;
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bits<5> Rd;
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bits<5> Rs;
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bits<8> s8;
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let IClass = 0b0111;
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let Inst{27-24} = 0b0011;
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let Inst{22} = 0b1;
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let Inst{21} = IsNeg;
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let Inst{20-16} = Rs;
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let Inst{13} = 0b1;
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let Inst{12-5} = s8;
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let Inst{4-0} = Rd;
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}
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def A4_rcmpeqi : T_RCMP_EQ_ri<"cmp.eq", 0>;
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def A4_rcmpneqi : T_RCMP_EQ_ri<"!cmp.eq", 1>;
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//===----------------------------------------------------------------------===//
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// ALU32 -
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// ALU32/PERM +
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//===----------------------------------------------------------------------===//
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// Combine a word and an immediate into a register pair.
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let hasSideEffects = 0, isExtentSigned = 1, isExtendable = 1,
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opExtentBits = 8 in
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class T_Combine1 <bits<2> MajOp, dag ins, string AsmStr>
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: ALU32Inst <(outs DoubleRegs:$Rdd), ins, AsmStr> {
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bits<5> Rdd;
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bits<5> Rs;
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bits<8> s8;
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let IClass = 0b0111;
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let Inst{27-24} = 0b0011;
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let Inst{22-21} = MajOp;
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let Inst{20-16} = Rs;
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let Inst{13} = 0b1;
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let Inst{12-5} = s8;
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let Inst{4-0} = Rdd;
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}
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let opExtendable = 2 in
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def A4_combineri : T_Combine1<0b00, (ins IntRegs:$Rs, s8_0Ext:$s8),
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"$Rdd = combine($Rs, #$s8)">;
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let opExtendable = 1 in
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def A4_combineir : T_Combine1<0b01, (ins s8_0Ext:$s8, IntRegs:$Rs),
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"$Rdd = combine(#$s8, $Rs)">;
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// A4_combineii: Set two small immediates.
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let hasSideEffects = 0, isExtendable = 1, opExtentBits = 6, opExtendable = 2 in
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def A4_combineii: ALU32Inst<(outs DoubleRegs:$Rdd), (ins s8_0Imm:$s8, u6_0Ext:$U6),
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"$Rdd = combine(#$s8, #$U6)"> {
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bits<5> Rdd;
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bits<8> s8;
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bits<6> U6;
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let IClass = 0b0111;
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let Inst{27-23} = 0b11001;
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let Inst{20-16} = U6{5-1};
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let Inst{13} = U6{0};
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let Inst{12-5} = s8;
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let Inst{4-0} = Rdd;
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}
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//===----------------------------------------------------------------------===//
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// ALU32/PERM -
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// LD +
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Template class for load instructions with Absolute set addressing mode.
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//===----------------------------------------------------------------------===//
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let isExtended = 1, opExtendable = 2, opExtentBits = 6, addrMode = AbsoluteSet,
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hasSideEffects = 0 in
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class T_LD_abs_set<string mnemonic, RegisterClass RC, bits<4>MajOp>:
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LDInst<(outs RC:$dst1, IntRegs:$dst2),
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(ins u6_0Ext:$addr),
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"$dst1 = "#mnemonic#"($dst2 = #$addr)",
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[]> {
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bits<7> name;
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bits<5> dst1;
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bits<5> dst2;
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bits<6> addr;
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let IClass = 0b1001;
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let Inst{27-25} = 0b101;
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let Inst{24-21} = MajOp;
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let Inst{13-12} = 0b01;
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let Inst{4-0} = dst1;
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let Inst{20-16} = dst2;
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let Inst{11-8} = addr{5-2};
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let Inst{6-5} = addr{1-0};
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}
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let accessSize = ByteAccess, hasNewValue = 1 in {
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def L4_loadrb_ap : T_LD_abs_set <"memb", IntRegs, 0b1000>;
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def L4_loadrub_ap : T_LD_abs_set <"memub", IntRegs, 0b1001>;
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}
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let accessSize = HalfWordAccess, hasNewValue = 1 in {
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def L4_loadrh_ap : T_LD_abs_set <"memh", IntRegs, 0b1010>;
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def L4_loadruh_ap : T_LD_abs_set <"memuh", IntRegs, 0b1011>;
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def L4_loadbsw2_ap : T_LD_abs_set <"membh", IntRegs, 0b0001>;
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def L4_loadbzw2_ap : T_LD_abs_set <"memubh", IntRegs, 0b0011>;
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}
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let accessSize = WordAccess, hasNewValue = 1 in
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def L4_loadri_ap : T_LD_abs_set <"memw", IntRegs, 0b1100>;
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let accessSize = WordAccess in {
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def L4_loadbzw4_ap : T_LD_abs_set <"memubh", DoubleRegs, 0b0101>;
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def L4_loadbsw4_ap : T_LD_abs_set <"membh", DoubleRegs, 0b0111>;
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}
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let accessSize = DoubleWordAccess in
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def L4_loadrd_ap : T_LD_abs_set <"memd", DoubleRegs, 0b1110>;
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let accessSize = ByteAccess in
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def L4_loadalignb_ap : T_LD_abs_set <"memb_fifo", DoubleRegs, 0b0100>;
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let accessSize = HalfWordAccess in
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def L4_loadalignh_ap : T_LD_abs_set <"memh_fifo", DoubleRegs, 0b0010>;
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// Load - Indirect with long offset
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let InputType = "imm", addrMode = BaseLongOffset, isExtended = 1,
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opExtentBits = 6, opExtendable = 3 in
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class T_LoadAbsReg <string mnemonic, string CextOp, RegisterClass RC,
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bits<4> MajOp>
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: LDInst <(outs RC:$dst), (ins IntRegs:$src1, u2_0Imm:$src2, u6_0Ext:$src3),
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"$dst = "#mnemonic#"($src1<<#$src2 + #$src3)",
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[] >, ImmRegShl {
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bits<5> dst;
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bits<5> src1;
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bits<2> src2;
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bits<6> src3;
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let CextOpcode = CextOp;
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let hasNewValue = !if (!eq(!cast<string>(RC), "DoubleRegs"), 0, 1);
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let IClass = 0b1001;
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let Inst{27-25} = 0b110;
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let Inst{24-21} = MajOp;
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let Inst{20-16} = src1;
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let Inst{13} = src2{1};
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let Inst{12} = 0b1;
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let Inst{11-8} = src3{5-2};
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let Inst{7} = src2{0};
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let Inst{6-5} = src3{1-0};
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let Inst{4-0} = dst;
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}
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let accessSize = ByteAccess in {
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def L4_loadrb_ur : T_LoadAbsReg<"memb", "LDrib", IntRegs, 0b1000>;
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def L4_loadrub_ur : T_LoadAbsReg<"memub", "LDriub", IntRegs, 0b1001>;
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def L4_loadalignb_ur : T_LoadAbsReg<"memb_fifo", "LDrib_fifo",
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DoubleRegs, 0b0100>;
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}
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let accessSize = HalfWordAccess in {
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def L4_loadrh_ur : T_LoadAbsReg<"memh", "LDrih", IntRegs, 0b1010>;
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def L4_loadruh_ur : T_LoadAbsReg<"memuh", "LDriuh", IntRegs, 0b1011>;
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def L4_loadbsw2_ur : T_LoadAbsReg<"membh", "LDribh2", IntRegs, 0b0001>;
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def L4_loadbzw2_ur : T_LoadAbsReg<"memubh", "LDriubh2", IntRegs, 0b0011>;
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def L4_loadalignh_ur : T_LoadAbsReg<"memh_fifo", "LDrih_fifo",
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DoubleRegs, 0b0010>;
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}
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let accessSize = WordAccess in {
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def L4_loadri_ur : T_LoadAbsReg<"memw", "LDriw", IntRegs, 0b1100>;
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def L4_loadbsw4_ur : T_LoadAbsReg<"membh", "LDribh4", DoubleRegs, 0b0111>;
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def L4_loadbzw4_ur : T_LoadAbsReg<"memubh", "LDriubh4", DoubleRegs, 0b0101>;
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}
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let accessSize = DoubleWordAccess in
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def L4_loadrd_ur : T_LoadAbsReg<"memd", "LDrid", DoubleRegs, 0b1110>;
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//===----------------------------------------------------------------------===//
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// Template classes for the non-predicated load instructions with
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// base + register offset addressing mode
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//===----------------------------------------------------------------------===//
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class T_load_rr <string mnemonic, RegisterClass RC, bits<3> MajOp>:
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LDInst<(outs RC:$dst), (ins IntRegs:$src1, IntRegs:$src2, u2_0Imm:$u2),
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"$dst = "#mnemonic#"($src1 + $src2<<#$u2)",
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[], "", V4LDST_tc_ld_SLOT01>, ImmRegShl, AddrModeRel {
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bits<5> dst;
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bits<5> src1;
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bits<5> src2;
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bits<2> u2;
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let IClass = 0b0011;
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let Inst{27-24} = 0b1010;
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let Inst{23-21} = MajOp;
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let Inst{20-16} = src1;
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let Inst{12-8} = src2;
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let Inst{13} = u2{1};
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let Inst{7} = u2{0};
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let Inst{4-0} = dst;
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}
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//===----------------------------------------------------------------------===//
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// Template classes for the predicated load instructions with
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// base + register offset addressing mode
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//===----------------------------------------------------------------------===//
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let isPredicated = 1 in
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class T_pload_rr <string mnemonic, RegisterClass RC, bits<3> MajOp,
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|
bit isNot, bit isPredNew>:
|
|
LDInst <(outs RC:$dst),
|
|
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2_0Imm:$u2),
|
|
!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
|
|
") ")#"$dst = "#mnemonic#"($src2+$src3<<#$u2)",
|
|
[], "", V4LDST_tc_ld_SLOT01>, AddrModeRel {
|
|
bits<5> dst;
|
|
bits<2> src1;
|
|
bits<5> src2;
|
|
bits<5> src3;
|
|
bits<2> u2;
|
|
|
|
let isPredicatedFalse = isNot;
|
|
let isPredicatedNew = isPredNew;
|
|
|
|
let IClass = 0b0011;
|
|
|
|
let Inst{27-26} = 0b00;
|
|
let Inst{25} = isPredNew;
|
|
let Inst{24} = isNot;
|
|
let Inst{23-21} = MajOp;
|
|
let Inst{20-16} = src2;
|
|
let Inst{12-8} = src3;
|
|
let Inst{13} = u2{1};
|
|
let Inst{7} = u2{0};
|
|
let Inst{6-5} = src1;
|
|
let Inst{4-0} = dst;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// multiclass for load instructions with base + register offset
|
|
// addressing mode
|
|
//===----------------------------------------------------------------------===//
|
|
let hasSideEffects = 0, addrMode = BaseRegOffset in
|
|
multiclass ld_idxd_shl <string mnemonic, string CextOp, RegisterClass RC,
|
|
bits<3> MajOp > {
|
|
let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl,
|
|
InputType = "reg" in {
|
|
let isPredicable = 1 in
|
|
def L4_#NAME#_rr : T_load_rr <mnemonic, RC, MajOp>;
|
|
|
|
// Predicated
|
|
def L4_p#NAME#t_rr : T_pload_rr <mnemonic, RC, MajOp, 0, 0>;
|
|
def L4_p#NAME#f_rr : T_pload_rr <mnemonic, RC, MajOp, 1, 0>;
|
|
|
|
// Predicated new
|
|
def L4_p#NAME#tnew_rr : T_pload_rr <mnemonic, RC, MajOp, 0, 1>;
|
|
def L4_p#NAME#fnew_rr : T_pload_rr <mnemonic, RC, MajOp, 1, 1>;
|
|
}
|
|
}
|
|
|
|
let hasNewValue = 1, accessSize = ByteAccess in {
|
|
defm loadrb : ld_idxd_shl<"memb", "LDrib", IntRegs, 0b000>;
|
|
defm loadrub : ld_idxd_shl<"memub", "LDriub", IntRegs, 0b001>;
|
|
}
|
|
|
|
let hasNewValue = 1, accessSize = HalfWordAccess in {
|
|
defm loadrh : ld_idxd_shl<"memh", "LDrih", IntRegs, 0b010>;
|
|
defm loadruh : ld_idxd_shl<"memuh", "LDriuh", IntRegs, 0b011>;
|
|
}
|
|
|
|
let hasNewValue = 1, accessSize = WordAccess in
|
|
defm loadri : ld_idxd_shl<"memw", "LDriw", IntRegs, 0b100>;
|
|
|
|
let accessSize = DoubleWordAccess in
|
|
defm loadrd : ld_idxd_shl<"memd", "LDrid", DoubleRegs, 0b110>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// LD -
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// ST +
|
|
//===----------------------------------------------------------------------===//
|
|
///
|
|
//===----------------------------------------------------------------------===//
|
|
// Template class for store instructions with Absolute set addressing mode.
|
|
//===----------------------------------------------------------------------===//
|
|
let isExtended = 1, opExtendable = 1, opExtentBits = 6,
|
|
addrMode = AbsoluteSet in
|
|
class T_ST_absset <string mnemonic, string BaseOp, RegisterClass RC,
|
|
bits<3> MajOp, MemAccessSize AccessSz, bit isHalf = 0>
|
|
: STInst<(outs IntRegs:$dst),
|
|
(ins u6_0Ext:$addr, RC:$src),
|
|
mnemonic#"($dst = #$addr) = $src"#!if(isHalf, ".h","")>, NewValueRel {
|
|
bits<5> dst;
|
|
bits<6> addr;
|
|
bits<5> src;
|
|
let accessSize = AccessSz;
|
|
let BaseOpcode = BaseOp#"_AbsSet";
|
|
|
|
// Store upper-half and store doubleword cannot be NV.
|
|
let isNVStorable = !if (!eq(mnemonic, "memd"), 0, !if(isHalf,0,1));
|
|
|
|
let IClass = 0b1010;
|
|
|
|
let Inst{27-24} = 0b1011;
|
|
let Inst{23-21} = MajOp;
|
|
let Inst{20-16} = dst;
|
|
let Inst{13} = 0b0;
|
|
let Inst{12-8} = src;
|
|
let Inst{7} = 0b1;
|
|
let Inst{5-0} = addr;
|
|
}
|
|
|
|
def S4_storerb_ap : T_ST_absset <"memb", "STrib", IntRegs, 0b000, ByteAccess>;
|
|
def S4_storerh_ap : T_ST_absset <"memh", "STrih", IntRegs, 0b010,
|
|
HalfWordAccess>;
|
|
def S4_storeri_ap : T_ST_absset <"memw", "STriw", IntRegs, 0b100, WordAccess>;
|
|
|
|
let isNVStorable = 0 in {
|
|
def S4_storerf_ap : T_ST_absset <"memh", "STrif", IntRegs,
|
|
0b011, HalfWordAccess, 1>;
|
|
def S4_storerd_ap : T_ST_absset <"memd", "STrid", DoubleRegs,
|
|
0b110, DoubleWordAccess>;
|
|
}
|
|
|
|
let opExtendable = 1, isNewValue = 1, isNVStore = 1, opNewValue = 2,
|
|
isExtended = 1, opExtentBits= 6 in
|
|
class T_ST_absset_nv <string mnemonic, string BaseOp, bits<2> MajOp,
|
|
MemAccessSize AccessSz >
|
|
: NVInst <(outs IntRegs:$dst),
|
|
(ins u6_0Ext:$addr, IntRegs:$src),
|
|
mnemonic#"($dst = #$addr) = $src.new">, NewValueRel {
|
|
bits<5> dst;
|
|
bits<6> addr;
|
|
bits<3> src;
|
|
let accessSize = AccessSz;
|
|
let BaseOpcode = BaseOp#"_AbsSet";
|
|
|
|
let IClass = 0b1010;
|
|
|
|
let Inst{27-21} = 0b1011101;
|
|
let Inst{20-16} = dst;
|
|
let Inst{13-11} = 0b000;
|
|
let Inst{12-11} = MajOp;
|
|
let Inst{10-8} = src;
|
|
let Inst{7} = 0b1;
|
|
let Inst{5-0} = addr;
|
|
}
|
|
|
|
let mayStore = 1, addrMode = AbsoluteSet in {
|
|
def S4_storerbnew_ap : T_ST_absset_nv <"memb", "STrib", 0b00, ByteAccess>;
|
|
def S4_storerhnew_ap : T_ST_absset_nv <"memh", "STrih", 0b01, HalfWordAccess>;
|
|
def S4_storerinew_ap : T_ST_absset_nv <"memw", "STriw", 0b10, WordAccess>;
|
|
}
|
|
|
|
let isExtended = 1, opExtendable = 2, opExtentBits = 6, InputType = "imm",
|
|
addrMode = BaseLongOffset, AddedComplexity = 40 in
|
|
class T_StoreAbsReg <string mnemonic, string CextOp, RegisterClass RC,
|
|
bits<3> MajOp, MemAccessSize AccessSz, bit isHalf = 0>
|
|
: STInst<(outs),
|
|
(ins IntRegs:$src1, u2_0Imm:$src2, u6_0Ext:$src3, RC:$src4),
|
|
mnemonic#"($src1<<#$src2 + #$src3) = $src4"#!if(isHalf, ".h",""),
|
|
[]>, ImmRegShl, NewValueRel {
|
|
|
|
bits<5> src1;
|
|
bits<2> src2;
|
|
bits<6> src3;
|
|
bits<5> src4;
|
|
|
|
let accessSize = AccessSz;
|
|
let CextOpcode = CextOp;
|
|
let BaseOpcode = CextOp#"_shl";
|
|
|
|
// Store upper-half and store doubleword cannot be NV.
|
|
let isNVStorable = !if (!eq(mnemonic, "memd"), 0, !if(isHalf,0,1));
|
|
|
|
let IClass = 0b1010;
|
|
|
|
let Inst{27-24} =0b1101;
|
|
let Inst{23-21} = MajOp;
|
|
let Inst{20-16} = src1;
|
|
let Inst{13} = src2{1};
|
|
let Inst{12-8} = src4;
|
|
let Inst{7} = 0b1;
|
|
let Inst{6} = src2{0};
|
|
let Inst{5-0} = src3;
|
|
}
|
|
|
|
def S4_storerb_ur : T_StoreAbsReg <"memb", "STrib", IntRegs, 0b000, ByteAccess>;
|
|
def S4_storerh_ur : T_StoreAbsReg <"memh", "STrih", IntRegs, 0b010,
|
|
HalfWordAccess>;
|
|
def S4_storerf_ur : T_StoreAbsReg <"memh", "STrif", IntRegs, 0b011,
|
|
HalfWordAccess, 1>;
|
|
def S4_storeri_ur : T_StoreAbsReg <"memw", "STriw", IntRegs, 0b100, WordAccess>;
|
|
def S4_storerd_ur : T_StoreAbsReg <"memd", "STrid", DoubleRegs, 0b110,
|
|
DoubleWordAccess>;
|
|
|
|
let mayStore = 1, isNVStore = 1, isExtended = 1, addrMode = BaseLongOffset,
|
|
opExtentBits = 6, isNewValue = 1, opNewValue = 3, opExtendable = 2 in
|
|
class T_StoreAbsRegNV <string mnemonic, string CextOp, bits<2> MajOp,
|
|
MemAccessSize AccessSz>
|
|
: NVInst <(outs ),
|
|
(ins IntRegs:$src1, u2_0Imm:$src2, u6_0Ext:$src3, IntRegs:$src4),
|
|
mnemonic#"($src1<<#$src2 + #$src3) = $src4.new">, NewValueRel {
|
|
bits<5> src1;
|
|
bits<2> src2;
|
|
bits<6> src3;
|
|
bits<3> src4;
|
|
|
|
let CextOpcode = CextOp;
|
|
let BaseOpcode = CextOp#"_shl";
|
|
let IClass = 0b1010;
|
|
|
|
let Inst{27-21} = 0b1101101;
|
|
let Inst{12-11} = 0b00;
|
|
let Inst{7} = 0b1;
|
|
let Inst{20-16} = src1;
|
|
let Inst{13} = src2{1};
|
|
let Inst{12-11} = MajOp;
|
|
let Inst{10-8} = src4;
|
|
let Inst{6} = src2{0};
|
|
let Inst{5-0} = src3;
|
|
}
|
|
|
|
def S4_storerbnew_ur : T_StoreAbsRegNV <"memb", "STrib", 0b00, ByteAccess>;
|
|
def S4_storerhnew_ur : T_StoreAbsRegNV <"memh", "STrih", 0b01, HalfWordAccess>;
|
|
def S4_storerinew_ur : T_StoreAbsRegNV <"memw", "STriw", 0b10, WordAccess>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Template classes for the non-predicated store instructions with
|
|
// base + register offset addressing mode
|
|
//===----------------------------------------------------------------------===//
|
|
let isPredicable = 1 in
|
|
class T_store_rr <string mnemonic, RegisterClass RC, bits<3> MajOp, bit isH>
|
|
: STInst < (outs ), (ins IntRegs:$Rs, IntRegs:$Ru, u2_0Imm:$u2, RC:$Rt),
|
|
mnemonic#"($Rs + $Ru<<#$u2) = $Rt"#!if(isH, ".h",""),
|
|
[],"",V4LDST_tc_st_SLOT01>, ImmRegShl, AddrModeRel {
|
|
|
|
bits<5> Rs;
|
|
bits<5> Ru;
|
|
bits<2> u2;
|
|
bits<5> Rt;
|
|
|
|
// Store upper-half and store doubleword cannot be NV.
|
|
let isNVStorable = !if (!eq(mnemonic, "memd"), 0, !if(isH,0,1));
|
|
|
|
let IClass = 0b0011;
|
|
|
|
let Inst{27-24} = 0b1011;
|
|
let Inst{23-21} = MajOp;
|
|
let Inst{20-16} = Rs;
|
|
let Inst{12-8} = Ru;
|
|
let Inst{13} = u2{1};
|
|
let Inst{7} = u2{0};
|
|
let Inst{4-0} = Rt;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Template classes for the predicated store instructions with
|
|
// base + register offset addressing mode
|
|
//===----------------------------------------------------------------------===//
|
|
let isPredicated = 1 in
|
|
class T_pstore_rr <string mnemonic, RegisterClass RC, bits<3> MajOp,
|
|
bit isNot, bit isPredNew, bit isH>
|
|
: STInst <(outs),
|
|
(ins PredRegs:$Pv, IntRegs:$Rs, IntRegs:$Ru, u2_0Imm:$u2, RC:$Rt),
|
|
|
|
!if(isNot, "if (!$Pv", "if ($Pv")#!if(isPredNew, ".new) ",
|
|
") ")#mnemonic#"($Rs+$Ru<<#$u2) = $Rt"#!if(isH, ".h",""),
|
|
[], "", V4LDST_tc_st_SLOT01> , AddrModeRel{
|
|
bits<2> Pv;
|
|
bits<5> Rs;
|
|
bits<5> Ru;
|
|
bits<2> u2;
|
|
bits<5> Rt;
|
|
|
|
let isPredicatedFalse = isNot;
|
|
let isPredicatedNew = isPredNew;
|
|
// Store upper-half and store doubleword cannot be NV.
|
|
let isNVStorable = !if (!eq(mnemonic, "memd"), 0, !if(isH,0,1));
|
|
|
|
let IClass = 0b0011;
|
|
|
|
let Inst{27-26} = 0b01;
|
|
let Inst{25} = isPredNew;
|
|
let Inst{24} = isNot;
|
|
let Inst{23-21} = MajOp;
|
|
let Inst{20-16} = Rs;
|
|
let Inst{12-8} = Ru;
|
|
let Inst{13} = u2{1};
|
|
let Inst{7} = u2{0};
|
|
let Inst{6-5} = Pv;
|
|
let Inst{4-0} = Rt;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Template classes for the new-value store instructions with
|
|
// base + register offset addressing mode
|
|
//===----------------------------------------------------------------------===//
|
|
let isPredicable = 1, isNewValue = 1, opNewValue = 3 in
|
|
class T_store_new_rr <string mnemonic, bits<2> MajOp> :
|
|
NVInst < (outs ), (ins IntRegs:$Rs, IntRegs:$Ru, u2_0Imm:$u2, IntRegs:$Nt),
|
|
mnemonic#"($Rs + $Ru<<#$u2) = $Nt.new",
|
|
[],"",V4LDST_tc_st_SLOT0>, ImmRegShl, AddrModeRel {
|
|
|
|
bits<5> Rs;
|
|
bits<5> Ru;
|
|
bits<2> u2;
|
|
bits<3> Nt;
|
|
|
|
let IClass = 0b0011;
|
|
|
|
let Inst{27-21} = 0b1011101;
|
|
let Inst{20-16} = Rs;
|
|
let Inst{12-8} = Ru;
|
|
let Inst{13} = u2{1};
|
|
let Inst{7} = u2{0};
|
|
let Inst{4-3} = MajOp;
|
|
let Inst{2-0} = Nt;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Template classes for the predicated new-value store instructions with
|
|
// base + register offset addressing mode
|
|
//===----------------------------------------------------------------------===//
|
|
let isPredicated = 1, isNewValue = 1, opNewValue = 4 in
|
|
class T_pstore_new_rr <string mnemonic, bits<2> MajOp, bit isNot, bit isPredNew>
|
|
: NVInst<(outs),
|
|
(ins PredRegs:$Pv, IntRegs:$Rs, IntRegs:$Ru, u2_0Imm:$u2, IntRegs:$Nt),
|
|
!if(isNot, "if (!$Pv", "if ($Pv")#!if(isPredNew, ".new) ",
|
|
") ")#mnemonic#"($Rs+$Ru<<#$u2) = $Nt.new",
|
|
[], "", V4LDST_tc_st_SLOT0>, AddrModeRel {
|
|
bits<2> Pv;
|
|
bits<5> Rs;
|
|
bits<5> Ru;
|
|
bits<2> u2;
|
|
bits<3> Nt;
|
|
|
|
let isPredicatedFalse = isNot;
|
|
let isPredicatedNew = isPredNew;
|
|
|
|
let IClass = 0b0011;
|
|
let Inst{27-26} = 0b01;
|
|
let Inst{25} = isPredNew;
|
|
let Inst{24} = isNot;
|
|
let Inst{23-21} = 0b101;
|
|
let Inst{20-16} = Rs;
|
|
let Inst{12-8} = Ru;
|
|
let Inst{13} = u2{1};
|
|
let Inst{7} = u2{0};
|
|
let Inst{6-5} = Pv;
|
|
let Inst{4-3} = MajOp;
|
|
let Inst{2-0} = Nt;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// multiclass for store instructions with base + register offset addressing
|
|
// mode
|
|
//===----------------------------------------------------------------------===//
|
|
let isNVStorable = 1 in
|
|
multiclass ST_Idxd_shl<string mnemonic, string CextOp, RegisterClass RC,
|
|
bits<3> MajOp, bit isH = 0> {
|
|
let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
|
|
def S4_#NAME#_rr : T_store_rr <mnemonic, RC, MajOp, isH>;
|
|
|
|
// Predicated
|
|
def S4_p#NAME#t_rr : T_pstore_rr <mnemonic, RC, MajOp, 0, 0, isH>;
|
|
def S4_p#NAME#f_rr : T_pstore_rr <mnemonic, RC, MajOp, 1, 0, isH>;
|
|
|
|
// Predicated new
|
|
def S4_p#NAME#tnew_rr : T_pstore_rr <mnemonic, RC, MajOp, 0, 1, isH>;
|
|
def S4_p#NAME#fnew_rr : T_pstore_rr <mnemonic, RC, MajOp, 1, 1, isH>;
|
|
}
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// multiclass for new-value store instructions with base + register offset
|
|
// addressing mode.
|
|
//===----------------------------------------------------------------------===//
|
|
let mayStore = 1, isNVStore = 1 in
|
|
multiclass ST_Idxd_shl_nv <string mnemonic, string CextOp, RegisterClass RC,
|
|
bits<2> MajOp> {
|
|
let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
|
|
def S4_#NAME#new_rr : T_store_new_rr<mnemonic, MajOp>;
|
|
|
|
// Predicated
|
|
def S4_p#NAME#newt_rr : T_pstore_new_rr <mnemonic, MajOp, 0, 0>;
|
|
def S4_p#NAME#newf_rr : T_pstore_new_rr <mnemonic, MajOp, 1, 0>;
|
|
|
|
// Predicated new
|
|
def S4_p#NAME#newtnew_rr : T_pstore_new_rr <mnemonic, MajOp, 0, 1>;
|
|
def S4_p#NAME#newfnew_rr : T_pstore_new_rr <mnemonic, MajOp, 1, 1>;
|
|
}
|
|
}
|
|
|
|
let addrMode = BaseRegOffset, InputType = "reg", hasSideEffects = 0 in {
|
|
let accessSize = ByteAccess in
|
|
defm storerb: ST_Idxd_shl<"memb", "STrib", IntRegs, 0b000>,
|
|
ST_Idxd_shl_nv<"memb", "STrib", IntRegs, 0b00>;
|
|
|
|
let accessSize = HalfWordAccess in
|
|
defm storerh: ST_Idxd_shl<"memh", "STrih", IntRegs, 0b010>,
|
|
ST_Idxd_shl_nv<"memh", "STrih", IntRegs, 0b01>;
|
|
|
|
let accessSize = WordAccess in
|
|
defm storeri: ST_Idxd_shl<"memw", "STriw", IntRegs, 0b100>,
|
|
ST_Idxd_shl_nv<"memw", "STriw", IntRegs, 0b10>;
|
|
|
|
let isNVStorable = 0, accessSize = DoubleWordAccess in
|
|
defm storerd: ST_Idxd_shl<"memd", "STrid", DoubleRegs, 0b110>;
|
|
|
|
let isNVStorable = 0, accessSize = HalfWordAccess in
|
|
defm storerf: ST_Idxd_shl<"memh", "STrif", IntRegs, 0b011, 1>;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Template class
|
|
//===----------------------------------------------------------------------===//
|
|
let isPredicable = 1, isExtendable = 1, isExtentSigned = 1, opExtentBits = 8,
|
|
opExtendable = 2 in
|
|
class T_StoreImm <string mnemonic, Operand OffsetOp, bits<2> MajOp >
|
|
: STInst <(outs ), (ins IntRegs:$Rs, OffsetOp:$offset, s8_0Ext:$S8),
|
|
mnemonic#"($Rs+#$offset)=#$S8",
|
|
[], "", V4LDST_tc_st_SLOT01>,
|
|
ImmRegRel, PredNewRel {
|
|
bits<5> Rs;
|
|
bits<8> S8;
|
|
bits<8> offset;
|
|
bits<6> offsetBits;
|
|
|
|
string OffsetOpStr = !cast<string>(OffsetOp);
|
|
let offsetBits = !if (!eq(OffsetOpStr, "u6_2Imm"), offset{7-2},
|
|
!if (!eq(OffsetOpStr, "u6_1Imm"), offset{6-1},
|
|
/* u6_0Imm */ offset{5-0}));
|
|
|
|
let IClass = 0b0011;
|
|
|
|
let Inst{27-25} = 0b110;
|
|
let Inst{22-21} = MajOp;
|
|
let Inst{20-16} = Rs;
|
|
let Inst{12-7} = offsetBits;
|
|
let Inst{13} = S8{7};
|
|
let Inst{6-0} = S8{6-0};
|
|
}
|
|
|
|
let isPredicated = 1, isExtendable = 1, isExtentSigned = 1, opExtentBits = 6,
|
|
opExtendable = 3 in
|
|
class T_StoreImm_pred <string mnemonic, Operand OffsetOp, bits<2> MajOp,
|
|
bit isPredNot, bit isPredNew >
|
|
: STInst <(outs ),
|
|
(ins PredRegs:$Pv, IntRegs:$Rs, OffsetOp:$offset, s6_0Ext:$S6),
|
|
!if(isPredNot, "if (!$Pv", "if ($Pv")#!if(isPredNew, ".new) ",
|
|
") ")#mnemonic#"($Rs+#$offset)=#$S6",
|
|
[], "", V4LDST_tc_st_SLOT01>,
|
|
ImmRegRel, PredNewRel {
|
|
bits<2> Pv;
|
|
bits<5> Rs;
|
|
bits<6> S6;
|
|
bits<8> offset;
|
|
bits<6> offsetBits;
|
|
|
|
string OffsetOpStr = !cast<string>(OffsetOp);
|
|
let offsetBits = !if (!eq(OffsetOpStr, "u6_2Imm"), offset{7-2},
|
|
!if (!eq(OffsetOpStr, "u6_1Imm"), offset{6-1},
|
|
/* u6_0Imm */ offset{5-0}));
|
|
let isPredicatedNew = isPredNew;
|
|
let isPredicatedFalse = isPredNot;
|
|
|
|
let IClass = 0b0011;
|
|
|
|
let Inst{27-25} = 0b100;
|
|
let Inst{24} = isPredNew;
|
|
let Inst{23} = isPredNot;
|
|
let Inst{22-21} = MajOp;
|
|
let Inst{20-16} = Rs;
|
|
let Inst{13} = S6{5};
|
|
let Inst{12-7} = offsetBits;
|
|
let Inst{6-5} = Pv;
|
|
let Inst{4-0} = S6{4-0};
|
|
}
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// multiclass for store instructions with base + immediate offset
|
|
// addressing mode and immediate stored value.
|
|
// mem[bhw](Rx++#s4:3)=#s8
|
|
// if ([!]Pv[.new]) mem[bhw](Rx++#s4:3)=#s6
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
multiclass ST_Imm_Pred <string mnemonic, Operand OffsetOp, bits<2> MajOp,
|
|
bit PredNot> {
|
|
def _io : T_StoreImm_pred <mnemonic, OffsetOp, MajOp, PredNot, 0>;
|
|
// Predicate new
|
|
def new_io : T_StoreImm_pred <mnemonic, OffsetOp, MajOp, PredNot, 1>;
|
|
}
|
|
|
|
multiclass ST_Imm <string mnemonic, string CextOp, Operand OffsetOp,
|
|
bits<2> MajOp> {
|
|
let CextOpcode = CextOp, BaseOpcode = CextOp#_imm in {
|
|
def _io : T_StoreImm <mnemonic, OffsetOp, MajOp>;
|
|
|
|
defm t : ST_Imm_Pred <mnemonic, OffsetOp, MajOp, 0>;
|
|
defm f : ST_Imm_Pred <mnemonic, OffsetOp, MajOp, 1>;
|
|
}
|
|
}
|
|
|
|
let hasSideEffects = 0, addrMode = BaseImmOffset,
|
|
InputType = "imm" in {
|
|
let accessSize = ByteAccess in
|
|
defm S4_storeirb : ST_Imm<"memb", "STrib", u6_0Imm, 0b00>;
|
|
|
|
let accessSize = HalfWordAccess in
|
|
defm S4_storeirh : ST_Imm<"memh", "STrih", u6_1Imm, 0b01>;
|
|
|
|
let accessSize = WordAccess in
|
|
defm S4_storeiri : ST_Imm<"memw", "STriw", u6_2Imm, 0b10>;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===
|
|
// ST -
|
|
//===----------------------------------------------------------------------===
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// NV/ST +
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
let opNewValue = 2, opExtendable = 1, isExtentSigned = 1, isPredicable = 1 in
|
|
class T_store_io_nv <string mnemonic, RegisterClass RC,
|
|
Operand ImmOp, bits<2>MajOp>
|
|
: NVInst_V4 <(outs),
|
|
(ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
|
|
mnemonic#"($src1+#$src2) = $src3.new",
|
|
[],"",ST_tc_st_SLOT0> {
|
|
bits<5> src1;
|
|
bits<13> src2; // Actual address offset
|
|
bits<3> src3;
|
|
bits<11> offsetBits; // Represents offset encoding
|
|
|
|
let opExtentBits = !if (!eq(mnemonic, "memb"), 11,
|
|
!if (!eq(mnemonic, "memh"), 12,
|
|
!if (!eq(mnemonic, "memw"), 13, 0)));
|
|
|
|
let opExtentAlign = !if (!eq(mnemonic, "memb"), 0,
|
|
!if (!eq(mnemonic, "memh"), 1,
|
|
!if (!eq(mnemonic, "memw"), 2, 0)));
|
|
|
|
let offsetBits = !if (!eq(mnemonic, "memb"), src2{10-0},
|
|
!if (!eq(mnemonic, "memh"), src2{11-1},
|
|
!if (!eq(mnemonic, "memw"), src2{12-2}, 0)));
|
|
|
|
let IClass = 0b1010;
|
|
|
|
let Inst{27} = 0b0;
|
|
let Inst{26-25} = offsetBits{10-9};
|
|
let Inst{24-21} = 0b1101;
|
|
let Inst{20-16} = src1;
|
|
let Inst{13} = offsetBits{8};
|
|
let Inst{12-11} = MajOp;
|
|
let Inst{10-8} = src3;
|
|
let Inst{7-0} = offsetBits{7-0};
|
|
}
|
|
|
|
let opExtendable = 2, opNewValue = 3, isPredicated = 1 in
|
|
class T_pstore_io_nv <string mnemonic, RegisterClass RC, Operand predImmOp,
|
|
bits<2>MajOp, bit PredNot, bit isPredNew>
|
|
: NVInst_V4 <(outs),
|
|
(ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3, RC:$src4),
|
|
!if(PredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
|
|
") ")#mnemonic#"($src2+#$src3) = $src4.new",
|
|
[],"",V2LDST_tc_st_SLOT0> {
|
|
bits<2> src1;
|
|
bits<5> src2;
|
|
bits<9> src3;
|
|
bits<3> src4;
|
|
bits<6> offsetBits; // Represents offset encoding
|
|
|
|
let isPredicatedNew = isPredNew;
|
|
let isPredicatedFalse = PredNot;
|
|
let opExtentBits = !if (!eq(mnemonic, "memb"), 6,
|
|
!if (!eq(mnemonic, "memh"), 7,
|
|
!if (!eq(mnemonic, "memw"), 8, 0)));
|
|
|
|
let opExtentAlign = !if (!eq(mnemonic, "memb"), 0,
|
|
!if (!eq(mnemonic, "memh"), 1,
|
|
!if (!eq(mnemonic, "memw"), 2, 0)));
|
|
|
|
let offsetBits = !if (!eq(mnemonic, "memb"), src3{5-0},
|
|
!if (!eq(mnemonic, "memh"), src3{6-1},
|
|
!if (!eq(mnemonic, "memw"), src3{7-2}, 0)));
|
|
|
|
let IClass = 0b0100;
|
|
|
|
let Inst{27} = 0b0;
|
|
let Inst{26} = PredNot;
|
|
let Inst{25} = isPredNew;
|
|
let Inst{24-21} = 0b0101;
|
|
let Inst{20-16} = src2;
|
|
let Inst{13} = offsetBits{5};
|
|
let Inst{12-11} = MajOp;
|
|
let Inst{10-8} = src4;
|
|
let Inst{7-3} = offsetBits{4-0};
|
|
let Inst{2} = 0b0;
|
|
let Inst{1-0} = src1;
|
|
}
|
|
|
|
// multiclass for new-value store instructions with base + immediate offset.
|
|
//
|
|
let mayStore = 1, isNVStore = 1, isNewValue = 1, hasSideEffects = 0,
|
|
isExtendable = 1 in
|
|
multiclass ST_Idxd_nv<string mnemonic, string CextOp, RegisterClass RC,
|
|
Operand ImmOp, Operand predImmOp, bits<2> MajOp> {
|
|
|
|
let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
|
|
def S2_#NAME#new_io : T_store_io_nv <mnemonic, RC, ImmOp, MajOp>;
|
|
// Predicated
|
|
def S2_p#NAME#newt_io :T_pstore_io_nv <mnemonic, RC, predImmOp, MajOp, 0, 0>;
|
|
def S2_p#NAME#newf_io :T_pstore_io_nv <mnemonic, RC, predImmOp, MajOp, 1, 0>;
|
|
// Predicated new
|
|
def S4_p#NAME#newtnew_io :T_pstore_io_nv <mnemonic, RC, predImmOp,
|
|
MajOp, 0, 1>;
|
|
def S4_p#NAME#newfnew_io :T_pstore_io_nv <mnemonic, RC, predImmOp,
|
|
MajOp, 1, 1>;
|
|
}
|
|
}
|
|
|
|
let addrMode = BaseImmOffset, InputType = "imm" in {
|
|
let accessSize = ByteAccess in
|
|
defm storerb: ST_Idxd_nv<"memb", "STrib", IntRegs, s11_0Ext,
|
|
u6_0Ext, 0b00>, AddrModeRel;
|
|
|
|
let accessSize = HalfWordAccess, opExtentAlign = 1 in
|
|
defm storerh: ST_Idxd_nv<"memh", "STrih", IntRegs, s11_1Ext,
|
|
u6_1Ext, 0b01>, AddrModeRel;
|
|
|
|
let accessSize = WordAccess, opExtentAlign = 2 in
|
|
defm storeri: ST_Idxd_nv<"memw", "STriw", IntRegs, s11_2Ext,
|
|
u6_2Ext, 0b10>, AddrModeRel;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Post increment loads with register offset.
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
let hasNewValue = 1 in
|
|
def L2_loadbsw2_pr : T_load_pr <"membh", IntRegs, 0b0001, HalfWordAccess>;
|
|
|
|
def L2_loadbsw4_pr : T_load_pr <"membh", DoubleRegs, 0b0111, WordAccess>;
|
|
|
|
let hasSideEffects = 0, addrMode = PostInc in
|
|
class T_loadalign_pr <string mnemonic, bits<4> MajOp, MemAccessSize AccessSz>
|
|
: LDInstPI <(outs DoubleRegs:$dst, IntRegs:$_dst_),
|
|
(ins DoubleRegs:$src1, IntRegs:$src2, ModRegs:$src3),
|
|
"$dst = "#mnemonic#"($src2++$src3)", [],
|
|
"$src1 = $dst, $src2 = $_dst_"> {
|
|
bits<5> dst;
|
|
bits<5> src2;
|
|
bits<1> src3;
|
|
|
|
let accessSize = AccessSz;
|
|
let IClass = 0b1001;
|
|
|
|
let Inst{27-25} = 0b110;
|
|
let Inst{24-21} = MajOp;
|
|
let Inst{20-16} = src2;
|
|
let Inst{13} = src3;
|
|
let Inst{12} = 0b0;
|
|
let Inst{7} = 0b0;
|
|
let Inst{4-0} = dst;
|
|
}
|
|
|
|
def L2_loadalignb_pr : T_loadalign_pr <"memb_fifo", 0b0100, ByteAccess>;
|
|
def L2_loadalignh_pr : T_loadalign_pr <"memh_fifo", 0b0010, HalfWordAccess>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Template class for non-predicated post increment .new stores
|
|
// mem[bhwd](Rx++#s4:[0123])=Nt.new
|
|
//===----------------------------------------------------------------------===//
|
|
let isPredicable = 1, hasSideEffects = 0, addrMode = PostInc, isNVStore = 1,
|
|
isNewValue = 1, opNewValue = 3 in
|
|
class T_StorePI_nv <string mnemonic, Operand ImmOp, bits<2> MajOp >
|
|
: NVInstPI_V4 <(outs IntRegs:$_dst_),
|
|
(ins IntRegs:$src1, ImmOp:$offset, IntRegs:$src2),
|
|
mnemonic#"($src1++#$offset) = $src2.new",
|
|
[], "$src1 = $_dst_">,
|
|
AddrModeRel {
|
|
bits<5> src1;
|
|
bits<3> src2;
|
|
bits<7> offset;
|
|
bits<4> offsetBits;
|
|
|
|
string ImmOpStr = !cast<string>(ImmOp);
|
|
let offsetBits = !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
|
|
!if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
|
|
/* s4_0Imm */ offset{3-0}));
|
|
let IClass = 0b1010;
|
|
|
|
let Inst{27-21} = 0b1011101;
|
|
let Inst{20-16} = src1;
|
|
let Inst{13} = 0b0;
|
|
let Inst{12-11} = MajOp;
|
|
let Inst{10-8} = src2;
|
|
let Inst{7} = 0b0;
|
|
let Inst{6-3} = offsetBits;
|
|
let Inst{1} = 0b0;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Template class for predicated post increment .new stores
|
|
// if([!]Pv[.new]) mem[bhwd](Rx++#s4:[0123])=Nt.new
|
|
//===----------------------------------------------------------------------===//
|
|
let isPredicated = 1, hasSideEffects = 0, addrMode = PostInc, isNVStore = 1,
|
|
isNewValue = 1, opNewValue = 4 in
|
|
class T_StorePI_nv_pred <string mnemonic, Operand ImmOp,
|
|
bits<2> MajOp, bit isPredNot, bit isPredNew >
|
|
: NVInstPI_V4 <(outs IntRegs:$_dst_),
|
|
(ins PredRegs:$src1, IntRegs:$src2,
|
|
ImmOp:$offset, IntRegs:$src3),
|
|
!if(isPredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
|
|
") ")#mnemonic#"($src2++#$offset) = $src3.new",
|
|
[], "$src2 = $_dst_">,
|
|
AddrModeRel {
|
|
bits<2> src1;
|
|
bits<5> src2;
|
|
bits<3> src3;
|
|
bits<7> offset;
|
|
bits<4> offsetBits;
|
|
|
|
string ImmOpStr = !cast<string>(ImmOp);
|
|
let offsetBits = !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
|
|
!if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
|
|
/* s4_0Imm */ offset{3-0}));
|
|
let isPredicatedNew = isPredNew;
|
|
let isPredicatedFalse = isPredNot;
|
|
|
|
let IClass = 0b1010;
|
|
|
|
let Inst{27-21} = 0b1011101;
|
|
let Inst{20-16} = src2;
|
|
let Inst{13} = 0b1;
|
|
let Inst{12-11} = MajOp;
|
|
let Inst{10-8} = src3;
|
|
let Inst{7} = isPredNew;
|
|
let Inst{6-3} = offsetBits;
|
|
let Inst{2} = isPredNot;
|
|
let Inst{1-0} = src1;
|
|
}
|
|
|
|
multiclass ST_PostInc_Pred_nv<string mnemonic, Operand ImmOp,
|
|
bits<2> MajOp, bit PredNot> {
|
|
def _pi : T_StorePI_nv_pred <mnemonic, ImmOp, MajOp, PredNot, 0>;
|
|
|
|
// Predicate new
|
|
def new_pi : T_StorePI_nv_pred <mnemonic, ImmOp, MajOp, PredNot, 1>;
|
|
}
|
|
|
|
multiclass ST_PostInc_nv<string mnemonic, string BaseOp, Operand ImmOp,
|
|
bits<2> MajOp> {
|
|
let BaseOpcode = "POST_"#BaseOp in {
|
|
def S2_#NAME#_pi : T_StorePI_nv <mnemonic, ImmOp, MajOp>;
|
|
|
|
// Predicated
|
|
defm S2_p#NAME#t : ST_PostInc_Pred_nv <mnemonic, ImmOp, MajOp, 0>;
|
|
defm S2_p#NAME#f : ST_PostInc_Pred_nv <mnemonic, ImmOp, MajOp, 1>;
|
|
}
|
|
}
|
|
|
|
let accessSize = ByteAccess in
|
|
defm storerbnew: ST_PostInc_nv <"memb", "STrib", s4_0Imm, 0b00>;
|
|
|
|
let accessSize = HalfWordAccess in
|
|
defm storerhnew: ST_PostInc_nv <"memh", "STrih", s4_1Imm, 0b01>;
|
|
|
|
let accessSize = WordAccess in
|
|
defm storerinew: ST_PostInc_nv <"memw", "STriw", s4_2Imm, 0b10>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Template class for post increment .new stores with register offset
|
|
//===----------------------------------------------------------------------===//
|
|
let isNewValue = 1, mayStore = 1, isNVStore = 1, opNewValue = 3 in
|
|
class T_StorePI_RegNV <string mnemonic, bits<2> MajOp, MemAccessSize AccessSz>
|
|
: NVInstPI_V4 <(outs IntRegs:$_dst_),
|
|
(ins IntRegs:$src1, ModRegs:$src2, IntRegs:$src3),
|
|
#mnemonic#"($src1++$src2) = $src3.new",
|
|
[], "$src1 = $_dst_"> {
|
|
bits<5> src1;
|
|
bits<1> src2;
|
|
bits<3> src3;
|
|
let accessSize = AccessSz;
|
|
|
|
let IClass = 0b1010;
|
|
|
|
let Inst{27-21} = 0b1101101;
|
|
let Inst{20-16} = src1;
|
|
let Inst{13} = src2;
|
|
let Inst{12-11} = MajOp;
|
|
let Inst{10-8} = src3;
|
|
let Inst{7} = 0b0;
|
|
}
|
|
|
|
def S2_storerbnew_pr : T_StorePI_RegNV<"memb", 0b00, ByteAccess>;
|
|
def S2_storerhnew_pr : T_StorePI_RegNV<"memh", 0b01, HalfWordAccess>;
|
|
def S2_storerinew_pr : T_StorePI_RegNV<"memw", 0b10, WordAccess>;
|
|
|
|
// memb(Rx++#s4:0:circ(Mu))=Nt.new
|
|
// memb(Rx++I:circ(Mu))=Nt.new
|
|
// memb(Rx++Mu:brev)=Nt.new
|
|
// memh(Rx++#s4:1:circ(Mu))=Nt.new
|
|
// memh(Rx++I:circ(Mu))=Nt.new
|
|
// memh(Rx++Mu)=Nt.new
|
|
// memh(Rx++Mu:brev)=Nt.new
|
|
|
|
// memw(Rx++#s4:2:circ(Mu))=Nt.new
|
|
// memw(Rx++I:circ(Mu))=Nt.new
|
|
// memw(Rx++Mu)=Nt.new
|
|
// memw(Rx++Mu:brev)=Nt.new
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// NV/ST -
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// NV/J +
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// multiclass/template class for the new-value compare jumps with the register
|
|
// operands.
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 11,
|
|
opExtentAlign = 2 in
|
|
class NVJrr_template<string mnemonic, bits<3> majOp, bit NvOpNum,
|
|
bit isNegCond, bit isTak>
|
|
: NVInst_V4<(outs),
|
|
(ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
|
|
"if ("#!if(isNegCond, "!","")#mnemonic#
|
|
"($src1"#!if(!eq(NvOpNum, 0),".new, ",", ")#
|
|
"$src2"#!if(!eq(NvOpNum, 1),".new))","))")#" jump:"
|
|
#!if(isTak, "t","nt")#" $offset", []> {
|
|
|
|
bits<5> src1;
|
|
bits<5> src2;
|
|
bits<3> Ns; // New-Value Operand
|
|
bits<5> RegOp; // Non-New-Value Operand
|
|
bits<11> offset;
|
|
|
|
let isTaken = isTak;
|
|
let isPredicatedFalse = isNegCond;
|
|
let opNewValue{0} = NvOpNum;
|
|
|
|
let Ns = !if(!eq(NvOpNum, 0), src1{2-0}, src2{2-0});
|
|
let RegOp = !if(!eq(NvOpNum, 0), src2, src1);
|
|
|
|
let IClass = 0b0010;
|
|
let Inst{27-26} = 0b00;
|
|
let Inst{25-23} = majOp;
|
|
let Inst{22} = isNegCond;
|
|
let Inst{18-16} = Ns;
|
|
let Inst{13} = isTak;
|
|
let Inst{12-8} = RegOp;
|
|
let Inst{21-20} = offset{10-9};
|
|
let Inst{7-1} = offset{8-2};
|
|
}
|
|
|
|
|
|
multiclass NVJrr_cond<string mnemonic, bits<3> majOp, bit NvOpNum,
|
|
bit isNegCond> {
|
|
// Branch not taken:
|
|
def _nt: NVJrr_template<mnemonic, majOp, NvOpNum, isNegCond, 0>;
|
|
// Branch taken:
|
|
def _t : NVJrr_template<mnemonic, majOp, NvOpNum, isNegCond, 1>;
|
|
}
|
|
|
|
// NvOpNum = 0 -> First Operand is a new-value Register
|
|
// NvOpNum = 1 -> Second Operand is a new-value Register
|
|
|
|
multiclass NVJrr_base<string mnemonic, string BaseOp, bits<3> majOp,
|
|
bit NvOpNum> {
|
|
let BaseOpcode = BaseOp#_NVJ in {
|
|
defm _t_jumpnv : NVJrr_cond<mnemonic, majOp, NvOpNum, 0>; // True cond
|
|
defm _f_jumpnv : NVJrr_cond<mnemonic, majOp, NvOpNum, 1>; // False cond
|
|
}
|
|
}
|
|
|
|
// if ([!]cmp.eq(Ns.new,Rt)) jump:[n]t #r9:2
|
|
// if ([!]cmp.gt(Ns.new,Rt)) jump:[n]t #r9:2
|
|
// if ([!]cmp.gtu(Ns.new,Rt)) jump:[n]t #r9:2
|
|
// if ([!]cmp.gt(Rt,Ns.new)) jump:[n]t #r9:2
|
|
// if ([!]cmp.gtu(Rt,Ns.new)) jump:[n]t #r9:2
|
|
|
|
let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator = 1,
|
|
Defs = [PC], hasSideEffects = 0 in {
|
|
defm J4_cmpeq : NVJrr_base<"cmp.eq", "CMPEQ", 0b000, 0>, PredRel;
|
|
defm J4_cmpgt : NVJrr_base<"cmp.gt", "CMPGT", 0b001, 0>, PredRel;
|
|
defm J4_cmpgtu : NVJrr_base<"cmp.gtu", "CMPGTU", 0b010, 0>, PredRel;
|
|
defm J4_cmplt : NVJrr_base<"cmp.gt", "CMPLT", 0b011, 1>, PredRel;
|
|
defm J4_cmpltu : NVJrr_base<"cmp.gtu", "CMPLTU", 0b100, 1>, PredRel;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// multiclass/template class for the new-value compare jumps instruction
|
|
// with a register and an unsigned immediate (U5) operand.
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 11,
|
|
opExtentAlign = 2 in
|
|
class NVJri_template<string mnemonic, bits<3> majOp, bit isNegCond,
|
|
bit isTak>
|
|
: NVInst_V4<(outs),
|
|
(ins IntRegs:$src1, u5_0Imm:$src2, brtarget:$offset),
|
|
"if ("#!if(isNegCond, "!","")#mnemonic#"($src1.new, #$src2)) jump:"
|
|
#!if(isTak, "t","nt")#" $offset", []> {
|
|
|
|
let isTaken = isTak;
|
|
let isPredicatedFalse = isNegCond;
|
|
let isTaken = isTak;
|
|
|
|
bits<3> src1;
|
|
bits<5> src2;
|
|
bits<11> offset;
|
|
|
|
let IClass = 0b0010;
|
|
let Inst{26} = 0b1;
|
|
let Inst{25-23} = majOp;
|
|
let Inst{22} = isNegCond;
|
|
let Inst{18-16} = src1;
|
|
let Inst{13} = isTak;
|
|
let Inst{12-8} = src2;
|
|
let Inst{21-20} = offset{10-9};
|
|
let Inst{7-1} = offset{8-2};
|
|
}
|
|
|
|
multiclass NVJri_cond<string mnemonic, bits<3> majOp, bit isNegCond> {
|
|
// Branch not taken:
|
|
def _nt: NVJri_template<mnemonic, majOp, isNegCond, 0>;
|
|
// Branch taken:
|
|
def _t : NVJri_template<mnemonic, majOp, isNegCond, 1>;
|
|
}
|
|
|
|
multiclass NVJri_base<string mnemonic, string BaseOp, bits<3> majOp> {
|
|
let BaseOpcode = BaseOp#_NVJri in {
|
|
defm _t_jumpnv : NVJri_cond<mnemonic, majOp, 0>; // True Cond
|
|
defm _f_jumpnv : NVJri_cond<mnemonic, majOp, 1>; // False cond
|
|
}
|
|
}
|
|
|
|
// if ([!]cmp.eq(Ns.new,#U5)) jump:[n]t #r9:2
|
|
// if ([!]cmp.gt(Ns.new,#U5)) jump:[n]t #r9:2
|
|
// if ([!]cmp.gtu(Ns.new,#U5)) jump:[n]t #r9:2
|
|
|
|
let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator = 1,
|
|
Defs = [PC], hasSideEffects = 0 in {
|
|
defm J4_cmpeqi : NVJri_base<"cmp.eq", "CMPEQ", 0b000>, PredRel;
|
|
defm J4_cmpgti : NVJri_base<"cmp.gt", "CMPGT", 0b001>, PredRel;
|
|
defm J4_cmpgtui : NVJri_base<"cmp.gtu", "CMPGTU", 0b010>, PredRel;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// multiclass/template class for the new-value compare jumps instruction
|
|
// with a register and an hardcoded 0/-1 immediate value.
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 11,
|
|
opExtentAlign = 2 in
|
|
class NVJ_ConstImm_template<string mnemonic, bits<3> majOp, string ImmVal,
|
|
bit isNegCond, bit isTak>
|
|
: NVInst_V4<(outs),
|
|
(ins IntRegs:$src1, brtarget:$offset),
|
|
"if ("#!if(isNegCond, "!","")#mnemonic
|
|
#"($src1.new, #" # ImmVal # ")) jump:"
|
|
#!if(isTak, "t","nt")#" $offset", []> {
|
|
|
|
let isTaken = isTak;
|
|
let isPredicatedFalse = isNegCond;
|
|
let isTaken = isTak;
|
|
|
|
bits<3> src1;
|
|
bits<11> offset;
|
|
let IClass = 0b0010;
|
|
let Inst{26} = 0b1;
|
|
let Inst{25-23} = majOp;
|
|
let Inst{22} = isNegCond;
|
|
let Inst{18-16} = src1;
|
|
let Inst{13} = isTak;
|
|
let Inst{21-20} = offset{10-9};
|
|
let Inst{7-1} = offset{8-2};
|
|
}
|
|
|
|
multiclass NVJ_ConstImm_cond<string mnemonic, bits<3> majOp, string ImmVal,
|
|
bit isNegCond> {
|
|
// Branch not taken:
|
|
def _nt: NVJ_ConstImm_template<mnemonic, majOp, ImmVal, isNegCond, 0>;
|
|
// Branch taken:
|
|
def _t : NVJ_ConstImm_template<mnemonic, majOp, ImmVal, isNegCond, 1>;
|
|
}
|
|
|
|
multiclass NVJ_ConstImm_base<string mnemonic, string BaseOp, bits<3> majOp,
|
|
string ImmVal> {
|
|
let BaseOpcode = BaseOp#_NVJ_ConstImm in {
|
|
defm _t_jumpnv : NVJ_ConstImm_cond<mnemonic, majOp, ImmVal, 0>; // True
|
|
defm _f_jumpnv : NVJ_ConstImm_cond<mnemonic, majOp, ImmVal, 1>; // False
|
|
}
|
|
}
|
|
|
|
// if ([!]tstbit(Ns.new,#0)) jump:[n]t #r9:2
|
|
// if ([!]cmp.eq(Ns.new,#-1)) jump:[n]t #r9:2
|
|
// if ([!]cmp.gt(Ns.new,#-1)) jump:[n]t #r9:2
|
|
|
|
let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator=1,
|
|
Defs = [PC], hasSideEffects = 0 in {
|
|
defm J4_tstbit0 : NVJ_ConstImm_base<"tstbit", "TSTBIT", 0b011, "0">, PredRel;
|
|
defm J4_cmpeqn1 : NVJ_ConstImm_base<"cmp.eq", "CMPEQ", 0b100, "-1">, PredRel;
|
|
defm J4_cmpgtn1 : NVJ_ConstImm_base<"cmp.gt", "CMPGT", 0b101, "-1">, PredRel;
|
|
}
|
|
|
|
// J4_hintjumpr: Hint indirect conditional jump.
|
|
let isBranch = 1, isIndirectBranch = 1, hasSideEffects = 0 in
|
|
def J4_hintjumpr: JRInst <
|
|
(outs),
|
|
(ins IntRegs:$Rs),
|
|
"hintjr($Rs)"> {
|
|
bits<5> Rs;
|
|
let IClass = 0b0101;
|
|
let Inst{27-21} = 0b0010101;
|
|
let Inst{20-16} = Rs;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// NV/J -
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// CR +
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// PC-relative add
|
|
let hasNewValue = 1, isExtendable = 1, opExtendable = 1,
|
|
isExtentSigned = 0, opExtentBits = 6, hasSideEffects = 0, Uses = [PC] in
|
|
def C4_addipc : CRInst <(outs IntRegs:$Rd), (ins u6_0Ext:$u6),
|
|
"$Rd = add(pc, #$u6)", [], "", CR_tc_2_SLOT3 > {
|
|
bits<5> Rd;
|
|
bits<6> u6;
|
|
|
|
let IClass = 0b0110;
|
|
let Inst{27-16} = 0b101001001001;
|
|
let Inst{12-7} = u6;
|
|
let Inst{4-0} = Rd;
|
|
}
|
|
|
|
|
|
|
|
let hasSideEffects = 0 in
|
|
class T_LOGICAL_3OP<string MnOp1, string MnOp2, bits<2> OpBits, bit IsNeg>
|
|
: CRInst<(outs PredRegs:$Pd),
|
|
(ins PredRegs:$Ps, PredRegs:$Pt, PredRegs:$Pu),
|
|
"$Pd = " # MnOp1 # "($Ps, " # MnOp2 # "($Pt, " #
|
|
!if (IsNeg,"!","") # "$Pu))",
|
|
[], "", CR_tc_2early_SLOT23> {
|
|
bits<2> Pd;
|
|
bits<2> Ps;
|
|
bits<2> Pt;
|
|
bits<2> Pu;
|
|
|
|
let IClass = 0b0110;
|
|
let Inst{27-24} = 0b1011;
|
|
let Inst{23} = IsNeg;
|
|
let Inst{22-21} = OpBits;
|
|
let Inst{20} = 0b1;
|
|
let Inst{17-16} = Ps;
|
|
let Inst{13} = 0b0;
|
|
let Inst{9-8} = Pt;
|
|
let Inst{7-6} = Pu;
|
|
let Inst{1-0} = Pd;
|
|
}
|
|
|
|
def C4_and_and : T_LOGICAL_3OP<"and", "and", 0b00, 0>;
|
|
def C4_and_or : T_LOGICAL_3OP<"and", "or", 0b01, 0>;
|
|
def C4_or_and : T_LOGICAL_3OP<"or", "and", 0b10, 0>;
|
|
def C4_or_or : T_LOGICAL_3OP<"or", "or", 0b11, 0>;
|
|
def C4_and_andn : T_LOGICAL_3OP<"and", "and", 0b00, 1>;
|
|
def C4_and_orn : T_LOGICAL_3OP<"and", "or", 0b01, 1>;
|
|
def C4_or_andn : T_LOGICAL_3OP<"or", "and", 0b10, 1>;
|
|
def C4_or_orn : T_LOGICAL_3OP<"or", "or", 0b11, 1>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// CR -
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// XTYPE/ALU +
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Logical with-not instructions.
|
|
def A4_andnp : T_ALU64_logical<"and", 0b001, 1, 0, 1>;
|
|
def A4_ornp : T_ALU64_logical<"or", 0b011, 1, 0, 1>;
|
|
|
|
let hasNewValue = 1, hasSideEffects = 0 in
|
|
def S4_parity: ALU64Inst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
|
|
"$Rd = parity($Rs, $Rt)", [], "", ALU64_tc_2_SLOT23> {
|
|
bits<5> Rd;
|
|
bits<5> Rs;
|
|
bits<5> Rt;
|
|
|
|
let IClass = 0b1101;
|
|
let Inst{27-21} = 0b0101111;
|
|
let Inst{20-16} = Rs;
|
|
let Inst{12-8} = Rt;
|
|
let Inst{4-0} = Rd;
|
|
}
|
|
|
|
// Add and accumulate.
|
|
// Rd=add(Rs,add(Ru,#s6))
|
|
let isExtentSigned = 1, hasNewValue = 1, isExtendable = 1, opExtentBits = 6,
|
|
opExtendable = 3 in
|
|
def S4_addaddi : ALU64Inst <(outs IntRegs:$Rd),
|
|
(ins IntRegs:$Rs, IntRegs:$Ru, s6_0Ext:$s6),
|
|
"$Rd = add($Rs, add($Ru, #$s6))" , [],
|
|
"", ALU64_tc_2_SLOT23> {
|
|
bits<5> Rd;
|
|
bits<5> Rs;
|
|
bits<5> Ru;
|
|
bits<6> s6;
|
|
|
|
let IClass = 0b1101;
|
|
|
|
let Inst{27-23} = 0b10110;
|
|
let Inst{22-21} = s6{5-4};
|
|
let Inst{20-16} = Rs;
|
|
let Inst{13} = s6{3};
|
|
let Inst{12-8} = Rd;
|
|
let Inst{7-5} = s6{2-0};
|
|
let Inst{4-0} = Ru;
|
|
}
|
|
|
|
let isExtentSigned = 1, hasSideEffects = 0, hasNewValue = 1, isExtendable = 1,
|
|
opExtentBits = 6, opExtendable = 2 in
|
|
def S4_subaddi: ALU64Inst <(outs IntRegs:$Rd),
|
|
(ins IntRegs:$Rs, s6_0Ext:$s6, IntRegs:$Ru),
|
|
"$Rd = add($Rs, sub(#$s6, $Ru))",
|
|
[], "", ALU64_tc_2_SLOT23> {
|
|
bits<5> Rd;
|
|
bits<5> Rs;
|
|
bits<6> s6;
|
|
bits<5> Ru;
|
|
|
|
let IClass = 0b1101;
|
|
|
|
let Inst{27-23} = 0b10111;
|
|
let Inst{22-21} = s6{5-4};
|
|
let Inst{20-16} = Rs;
|
|
let Inst{13} = s6{3};
|
|
let Inst{12-8} = Rd;
|
|
let Inst{7-5} = s6{2-0};
|
|
let Inst{4-0} = Ru;
|
|
}
|
|
|
|
def S4_extractp_rp : T_S3op_64 < "extract", 0b11, 0b100, 0>;
|
|
def S4_extractp : T_S2op_extract <"extract", 0b1010, DoubleRegs, u6_0Imm>;
|
|
|
|
let hasNewValue = 1 in {
|
|
def S4_extract_rp : T_S3op_extract<"extract", 0b01>;
|
|
def S4_extract : T_S2op_extract <"extract", 0b1101, IntRegs, u5_0Imm>;
|
|
}
|
|
|
|
// Complex add/sub halfwords/words
|
|
let Defs = [USR_OVF] in {
|
|
def S4_vxaddsubh : T_S3op_64 < "vxaddsubh", 0b01, 0b100, 0, 1>;
|
|
def S4_vxaddsubw : T_S3op_64 < "vxaddsubw", 0b01, 0b000, 0, 1>;
|
|
def S4_vxsubaddh : T_S3op_64 < "vxsubaddh", 0b01, 0b110, 0, 1>;
|
|
def S4_vxsubaddw : T_S3op_64 < "vxsubaddw", 0b01, 0b010, 0, 1>;
|
|
}
|
|
|
|
let Defs = [USR_OVF] in {
|
|
def S4_vxaddsubhr : T_S3op_64 < "vxaddsubh", 0b11, 0b000, 0, 1, 1, 1>;
|
|
def S4_vxsubaddhr : T_S3op_64 < "vxsubaddh", 0b11, 0b010, 0, 1, 1, 1>;
|
|
}
|
|
|
|
let Itinerary = M_tc_3x_SLOT23, Defs = [USR_OVF] in {
|
|
def M4_mac_up_s1_sat: T_MType_acc_rr<"+= mpy", 0b011, 0b000, 0, [], 0, 1, 1>;
|
|
def M4_nac_up_s1_sat: T_MType_acc_rr<"-= mpy", 0b011, 0b001, 0, [], 0, 1, 1>;
|
|
}
|
|
|
|
// Logical xor with xor accumulation.
|
|
// Rxx^=xor(Rss,Rtt)
|
|
let hasSideEffects = 0 in
|
|
def M4_xor_xacc
|
|
: SInst <(outs DoubleRegs:$Rxx),
|
|
(ins DoubleRegs:$dst2, DoubleRegs:$Rss, DoubleRegs:$Rtt),
|
|
"$Rxx ^= xor($Rss, $Rtt)", [],
|
|
"$dst2 = $Rxx", S_3op_tc_1_SLOT23> {
|
|
bits<5> Rxx;
|
|
bits<5> Rss;
|
|
bits<5> Rtt;
|
|
|
|
let IClass = 0b1100;
|
|
|
|
let Inst{27-22} = 0b101010;
|
|
let Inst{20-16} = Rss;
|
|
let Inst{12-8} = Rtt;
|
|
let Inst{7-5} = 0b000;
|
|
let Inst{4-0} = Rxx;
|
|
}
|
|
|
|
// Rotate and reduce bytes
|
|
// Rdd=vrcrotate(Rss,Rt,#u2)
|
|
let hasSideEffects = 0 in
|
|
def S4_vrcrotate
|
|
: SInst <(outs DoubleRegs:$Rdd),
|
|
(ins DoubleRegs:$Rss, IntRegs:$Rt, u2_0Imm:$u2),
|
|
"$Rdd = vrcrotate($Rss, $Rt, #$u2)",
|
|
[], "", S_3op_tc_3x_SLOT23> {
|
|
bits<5> Rdd;
|
|
bits<5> Rss;
|
|
bits<5> Rt;
|
|
bits<2> u2;
|
|
|
|
let IClass = 0b1100;
|
|
|
|
let Inst{27-22} = 0b001111;
|
|
let Inst{20-16} = Rss;
|
|
let Inst{13} = u2{1};
|
|
let Inst{12-8} = Rt;
|
|
let Inst{7-6} = 0b11;
|
|
let Inst{5} = u2{0};
|
|
let Inst{4-0} = Rdd;
|
|
}
|
|
|
|
// Rotate and reduce bytes with accumulation
|
|
// Rxx+=vrcrotate(Rss,Rt,#u2)
|
|
let hasSideEffects = 0 in
|
|
def S4_vrcrotate_acc
|
|
: SInst <(outs DoubleRegs:$Rxx),
|
|
(ins DoubleRegs:$dst2, DoubleRegs:$Rss, IntRegs:$Rt, u2_0Imm:$u2),
|
|
"$Rxx += vrcrotate($Rss, $Rt, #$u2)", [],
|
|
"$dst2 = $Rxx", S_3op_tc_3x_SLOT23> {
|
|
bits<5> Rxx;
|
|
bits<5> Rss;
|
|
bits<5> Rt;
|
|
bits<2> u2;
|
|
|
|
let IClass = 0b1100;
|
|
|
|
let Inst{27-21} = 0b1011101;
|
|
let Inst{20-16} = Rss;
|
|
let Inst{13} = u2{1};
|
|
let Inst{12-8} = Rt;
|
|
let Inst{5} = u2{0};
|
|
let Inst{4-0} = Rxx;
|
|
}
|
|
|
|
// Vector reduce conditional negate halfwords
|
|
let hasSideEffects = 0 in
|
|
def S2_vrcnegh
|
|
: SInst <(outs DoubleRegs:$Rxx),
|
|
(ins DoubleRegs:$dst2, DoubleRegs:$Rss, IntRegs:$Rt),
|
|
"$Rxx += vrcnegh($Rss, $Rt)", [],
|
|
"$dst2 = $Rxx", S_3op_tc_3x_SLOT23> {
|
|
bits<5> Rxx;
|
|
bits<5> Rss;
|
|
bits<5> Rt;
|
|
|
|
let IClass = 0b1100;
|
|
|
|
let Inst{27-21} = 0b1011001;
|
|
let Inst{20-16} = Rss;
|
|
let Inst{13} = 0b1;
|
|
let Inst{12-8} = Rt;
|
|
let Inst{7-5} = 0b111;
|
|
let Inst{4-0} = Rxx;
|
|
}
|
|
|
|
// Split bitfield
|
|
def A4_bitspliti : T_S2op_2_di <"bitsplit", 0b110, 0b100>;
|
|
|
|
// Arithmetic/Convergent round
|
|
def A4_cround_ri : T_S2op_2_ii <"cround", 0b111, 0b000>;
|
|
|
|
def A4_round_ri : T_S2op_2_ii <"round", 0b111, 0b100>;
|
|
|
|
let Defs = [USR_OVF] in
|
|
def A4_round_ri_sat : T_S2op_2_ii <"round", 0b111, 0b110, 1>;
|
|
|
|
// Logical-logical words.
|
|
// Compound or-and -- Rx=or(Ru,and(Rx,#s10))
|
|
let isExtentSigned = 1, hasNewValue = 1, isExtendable = 1, opExtentBits = 10,
|
|
opExtendable = 3 in
|
|
def S4_or_andix:
|
|
ALU64Inst<(outs IntRegs:$Rx),
|
|
(ins IntRegs:$Ru, IntRegs:$_src_, s10_0Ext:$s10),
|
|
"$Rx = or($Ru, and($_src_, #$s10))" , [] ,
|
|
"$_src_ = $Rx", ALU64_tc_2_SLOT23> {
|
|
bits<5> Rx;
|
|
bits<5> Ru;
|
|
bits<10> s10;
|
|
|
|
let IClass = 0b1101;
|
|
|
|
let Inst{27-22} = 0b101001;
|
|
let Inst{20-16} = Rx;
|
|
let Inst{21} = s10{9};
|
|
let Inst{13-5} = s10{8-0};
|
|
let Inst{4-0} = Ru;
|
|
}
|
|
|
|
// Miscellaneous ALU64 instructions.
|
|
//
|
|
let hasNewValue = 1, hasSideEffects = 0 in
|
|
def A4_modwrapu: ALU64Inst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
|
|
"$Rd = modwrap($Rs, $Rt)", [], "", ALU64_tc_2_SLOT23> {
|
|
bits<5> Rd;
|
|
bits<5> Rs;
|
|
bits<5> Rt;
|
|
|
|
let IClass = 0b1101;
|
|
let Inst{27-21} = 0b0011111;
|
|
let Inst{20-16} = Rs;
|
|
let Inst{12-8} = Rt;
|
|
let Inst{7-5} = 0b111;
|
|
let Inst{4-0} = Rd;
|
|
}
|
|
|
|
let hasSideEffects = 0 in
|
|
def A4_bitsplit: ALU64Inst<(outs DoubleRegs:$Rd),
|
|
(ins IntRegs:$Rs, IntRegs:$Rt),
|
|
"$Rd = bitsplit($Rs, $Rt)", [], "", ALU64_tc_1_SLOT23> {
|
|
bits<5> Rd;
|
|
bits<5> Rs;
|
|
bits<5> Rt;
|
|
|
|
let IClass = 0b1101;
|
|
let Inst{27-24} = 0b0100;
|
|
let Inst{21} = 0b1;
|
|
let Inst{20-16} = Rs;
|
|
let Inst{12-8} = Rt;
|
|
let Inst{4-0} = Rd;
|
|
}
|
|
|
|
let hasSideEffects = 0 in
|
|
def dep_S2_packhl: ALU64Inst<(outs DoubleRegs:$Rd),
|
|
(ins IntRegs:$Rs, IntRegs:$Rt),
|
|
"$Rd = packhl($Rs, $Rt):deprecated", [], "", ALU64_tc_1_SLOT23> {
|
|
bits<5> Rd;
|
|
bits<5> Rs;
|
|
bits<5> Rt;
|
|
|
|
let IClass = 0b1101;
|
|
let Inst{27-24} = 0b0100;
|
|
let Inst{21} = 0b0;
|
|
let Inst{20-16} = Rs;
|
|
let Inst{12-8} = Rt;
|
|
let Inst{4-0} = Rd;
|
|
}
|
|
|
|
let hasNewValue = 1, hasSideEffects = 0 in
|
|
def dep_A2_addsat: ALU64Inst<(outs IntRegs:$Rd),
|
|
(ins IntRegs:$Rs, IntRegs:$Rt),
|
|
"$Rd = add($Rs, $Rt):sat:deprecated", [], "", ALU64_tc_2_SLOT23> {
|
|
bits<5> Rd;
|
|
bits<5> Rs;
|
|
bits<5> Rt;
|
|
|
|
let IClass = 0b1101;
|
|
let Inst{27-21} = 0b0101100;
|
|
let Inst{20-16} = Rs;
|
|
let Inst{12-8} = Rt;
|
|
let Inst{7} = 0b0;
|
|
let Inst{4-0} = Rd;
|
|
}
|
|
|
|
let hasNewValue = 1, hasSideEffects = 0 in
|
|
def dep_A2_subsat: ALU64Inst<(outs IntRegs:$Rd),
|
|
(ins IntRegs:$Rs, IntRegs:$Rt),
|
|
"$Rd = sub($Rs, $Rt):sat:deprecated", [], "", ALU64_tc_2_SLOT23> {
|
|
bits<5> Rd;
|
|
bits<5> Rs;
|
|
bits<5> Rt;
|
|
|
|
let IClass = 0b1101;
|
|
let Inst{27-21} = 0b0101100;
|
|
let Inst{20-16} = Rt;
|
|
let Inst{12-8} = Rs;
|
|
let Inst{7} = 0b1;
|
|
let Inst{4-0} = Rd;
|
|
}
|
|
|
|
// Rx[&|]=xor(Rs,Rt)
|
|
def M4_or_xor : T_MType_acc_rr < "|= xor", 0b110, 0b001, 0>;
|
|
def M4_and_xor : T_MType_acc_rr < "&= xor", 0b010, 0b010, 0>;
|
|
|
|
// Rx[&|^]=or(Rs,Rt)
|
|
def M4_xor_or : T_MType_acc_rr < "^= or", 0b110, 0b011, 0>;
|
|
|
|
let CextOpcode = "ORr_ORr" in
|
|
def M4_or_or : T_MType_acc_rr < "|= or", 0b110, 0b000, 0>;
|
|
def M4_and_or : T_MType_acc_rr < "&= or", 0b010, 0b001, 0>;
|
|
|
|
// Rx[&|^]=and(Rs,Rt)
|
|
def M4_xor_and : T_MType_acc_rr < "^= and", 0b110, 0b010, 0>;
|
|
|
|
let CextOpcode = "ORr_ANDr" in
|
|
def M4_or_and : T_MType_acc_rr < "|= and", 0b010, 0b011, 0>;
|
|
def M4_and_and : T_MType_acc_rr < "&= and", 0b010, 0b000, 0>;
|
|
|
|
// Rx[&|^]=and(Rs,~Rt)
|
|
def M4_xor_andn : T_MType_acc_rr < "^= and", 0b001, 0b010, 0, [], 1>;
|
|
def M4_or_andn : T_MType_acc_rr < "|= and", 0b001, 0b000, 0, [], 1>;
|
|
def M4_and_andn : T_MType_acc_rr < "&= and", 0b001, 0b001, 0, [], 1>;
|
|
|
|
// Compound or-or and or-and
|
|
let isExtentSigned = 1, InputType = "imm", hasNewValue = 1, isExtendable = 1,
|
|
opExtentBits = 10, opExtendable = 3 in
|
|
class T_CompOR <string mnemonic, bits<2> MajOp, SDNode OpNode>
|
|
: MInst_acc <(outs IntRegs:$Rx),
|
|
(ins IntRegs:$src1, IntRegs:$Rs, s10_0Ext:$s10),
|
|
"$Rx |= "#mnemonic#"($Rs, #$s10)", [],
|
|
"$src1 = $Rx", ALU64_tc_2_SLOT23>, ImmRegRel {
|
|
bits<5> Rx;
|
|
bits<5> Rs;
|
|
bits<10> s10;
|
|
|
|
let IClass = 0b1101;
|
|
|
|
let Inst{27-24} = 0b1010;
|
|
let Inst{23-22} = MajOp;
|
|
let Inst{20-16} = Rs;
|
|
let Inst{21} = s10{9};
|
|
let Inst{13-5} = s10{8-0};
|
|
let Inst{4-0} = Rx;
|
|
}
|
|
|
|
let CextOpcode = "ORr_ANDr" in
|
|
def S4_or_andi : T_CompOR <"and", 0b00, and>;
|
|
|
|
let CextOpcode = "ORr_ORr" in
|
|
def S4_or_ori : T_CompOR <"or", 0b10, or>;
|
|
|
|
// Modulo wrap
|
|
// Rd=modwrap(Rs,Rt)
|
|
// Round
|
|
// Rd=cround(Rs,#u5)
|
|
// Rd=cround(Rs,Rt)
|
|
// Rd=round(Rs,#u5)[:sat]
|
|
// Rd=round(Rs,Rt)[:sat]
|
|
// Vector reduce add unsigned halfwords
|
|
// Rd=vraddh(Rss,Rtt)
|
|
// Vector add bytes
|
|
// Rdd=vaddb(Rss,Rtt)
|
|
// Vector conditional negate
|
|
// Rdd=vcnegh(Rss,Rt)
|
|
// Rxx+=vrcnegh(Rss,Rt)
|
|
// Vector maximum bytes
|
|
// Rdd=vmaxb(Rtt,Rss)
|
|
// Vector reduce maximum halfwords
|
|
// Rxx=vrmaxh(Rss,Ru)
|
|
// Rxx=vrmaxuh(Rss,Ru)
|
|
// Vector reduce maximum words
|
|
// Rxx=vrmaxuw(Rss,Ru)
|
|
// Rxx=vrmaxw(Rss,Ru)
|
|
// Vector minimum bytes
|
|
// Rdd=vminb(Rtt,Rss)
|
|
// Vector reduce minimum halfwords
|
|
// Rxx=vrminh(Rss,Ru)
|
|
// Rxx=vrminuh(Rss,Ru)
|
|
// Vector reduce minimum words
|
|
// Rxx=vrminuw(Rss,Ru)
|
|
// Rxx=vrminw(Rss,Ru)
|
|
// Vector subtract bytes
|
|
// Rdd=vsubb(Rss,Rtt)
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// XTYPE/ALU -
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// XTYPE/BIT +
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Bit reverse
|
|
def S2_brevp : T_S2op_3 <"brev", 0b11, 0b110>;
|
|
|
|
// Bit count
|
|
def S2_ct0p : T_COUNT_LEADING_64<"ct0", 0b111, 0b010>;
|
|
def S2_ct1p : T_COUNT_LEADING_64<"ct1", 0b111, 0b100>;
|
|
def S4_clbpnorm : T_COUNT_LEADING_64<"normamt", 0b011, 0b000>;
|
|
|
|
let hasSideEffects = 0, hasNewValue = 1 in
|
|
def S4_clbaddi : SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, s6_0Imm:$s6),
|
|
"$Rd = add(clb($Rs), #$s6)", [], "", S_2op_tc_2_SLOT23> {
|
|
bits<5> Rs;
|
|
bits<5> Rd;
|
|
bits<6> s6;
|
|
let IClass = 0b1000;
|
|
let Inst{27-24} = 0b1100;
|
|
let Inst{23-21} = 0b001;
|
|
let Inst{20-16} = Rs;
|
|
let Inst{13-8} = s6;
|
|
let Inst{7-5} = 0b000;
|
|
let Inst{4-0} = Rd;
|
|
}
|
|
|
|
let hasSideEffects = 0, hasNewValue = 1 in
|
|
def S4_clbpaddi : SInst<(outs IntRegs:$Rd), (ins DoubleRegs:$Rs, s6_0Imm:$s6),
|
|
"$Rd = add(clb($Rs), #$s6)", [], "", S_2op_tc_2_SLOT23> {
|
|
bits<5> Rs;
|
|
bits<5> Rd;
|
|
bits<6> s6;
|
|
let IClass = 0b1000;
|
|
let Inst{27-24} = 0b1000;
|
|
let Inst{23-21} = 0b011;
|
|
let Inst{20-16} = Rs;
|
|
let Inst{13-8} = s6;
|
|
let Inst{7-5} = 0b010;
|
|
let Inst{4-0} = Rd;
|
|
}
|
|
|
|
|
|
// Bit test/set/clear
|
|
def S4_ntstbit_i : T_TEST_BIT_IMM<"!tstbit", 0b001>;
|
|
def S4_ntstbit_r : T_TEST_BIT_REG<"!tstbit", 1>;
|
|
|
|
def C4_nbitsset : T_TEST_BITS_REG<"!bitsset", 0b01, 1>;
|
|
def C4_nbitsclr : T_TEST_BITS_REG<"!bitsclr", 0b10, 1>;
|
|
def C4_nbitsclri : T_TEST_BITS_IMM<"!bitsclr", 0b10, 1>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// XTYPE/BIT -
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// XTYPE/MPY +
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Rd=add(#u6,mpyi(Rs,#U6)) -- Multiply by immed and add immed.
|
|
|
|
let hasNewValue = 1, isExtendable = 1, opExtentBits = 6, opExtendable = 1 in
|
|
def M4_mpyri_addi : MInst<(outs IntRegs:$Rd),
|
|
(ins u6_0Ext:$u6, IntRegs:$Rs, u6_0Imm:$U6),
|
|
"$Rd = add(#$u6, mpyi($Rs, #$U6))" , [],"",ALU64_tc_3x_SLOT23> {
|
|
bits<5> Rd;
|
|
bits<6> u6;
|
|
bits<5> Rs;
|
|
bits<6> U6;
|
|
|
|
let IClass = 0b1101;
|
|
|
|
let Inst{27-24} = 0b1000;
|
|
let Inst{23} = U6{5};
|
|
let Inst{22-21} = u6{5-4};
|
|
let Inst{20-16} = Rs;
|
|
let Inst{13} = u6{3};
|
|
let Inst{12-8} = Rd;
|
|
let Inst{7-5} = u6{2-0};
|
|
let Inst{4-0} = U6{4-0};
|
|
}
|
|
|
|
// Rd=add(#u6,mpyi(Rs,Rt))
|
|
let CextOpcode = "ADD_MPY", InputType = "imm", hasNewValue = 1,
|
|
isExtendable = 1, opExtentBits = 6, opExtendable = 1 in
|
|
def M4_mpyrr_addi : MInst <(outs IntRegs:$Rd),
|
|
(ins u6_0Ext:$u6, IntRegs:$Rs, IntRegs:$Rt),
|
|
"$Rd = add(#$u6, mpyi($Rs, $Rt))" , [], "", ALU64_tc_3x_SLOT23>, ImmRegRel {
|
|
bits<5> Rd;
|
|
bits<6> u6;
|
|
bits<5> Rs;
|
|
bits<5> Rt;
|
|
|
|
let IClass = 0b1101;
|
|
|
|
let Inst{27-23} = 0b01110;
|
|
let Inst{22-21} = u6{5-4};
|
|
let Inst{20-16} = Rs;
|
|
let Inst{13} = u6{3};
|
|
let Inst{12-8} = Rt;
|
|
let Inst{7-5} = u6{2-0};
|
|
let Inst{4-0} = Rd;
|
|
}
|
|
|
|
let hasNewValue = 1 in
|
|
class T_AddMpy <bit MajOp, PatLeaf ImmPred, dag ins>
|
|
: ALU64Inst <(outs IntRegs:$dst), ins,
|
|
"$dst = add($src1, mpyi("#!if(MajOp,"$src3, #$src2))",
|
|
"#$src2, $src3))"), [],
|
|
"", ALU64_tc_3x_SLOT23> {
|
|
bits<5> dst;
|
|
bits<5> src1;
|
|
bits<8> src2;
|
|
bits<5> src3;
|
|
|
|
let IClass = 0b1101;
|
|
|
|
bits<6> ImmValue = !if(MajOp, src2{5-0}, src2{7-2});
|
|
|
|
let Inst{27-24} = 0b1111;
|
|
let Inst{23} = MajOp;
|
|
let Inst{22-21} = ImmValue{5-4};
|
|
let Inst{20-16} = src3;
|
|
let Inst{13} = ImmValue{3};
|
|
let Inst{12-8} = dst;
|
|
let Inst{7-5} = ImmValue{2-0};
|
|
let Inst{4-0} = src1;
|
|
}
|
|
|
|
def M4_mpyri_addr_u2 : T_AddMpy<0b0, u6_2ImmPred,
|
|
(ins IntRegs:$src1, u6_2Imm:$src2, IntRegs:$src3)>;
|
|
|
|
let isExtendable = 1, opExtentBits = 6, opExtendable = 3,
|
|
CextOpcode = "ADD_MPY", InputType = "imm" in
|
|
def M4_mpyri_addr : T_AddMpy<0b1, u32_0ImmPred,
|
|
(ins IntRegs:$src1, IntRegs:$src3, u6_0Ext:$src2)>, ImmRegRel;
|
|
|
|
// Rx=add(Ru,mpyi(Rx,Rs))
|
|
let CextOpcode = "ADD_MPY", InputType = "reg", hasNewValue = 1 in
|
|
def M4_mpyrr_addr: MInst_acc <(outs IntRegs:$Rx),
|
|
(ins IntRegs:$Ru, IntRegs:$_src_, IntRegs:$Rs),
|
|
"$Rx = add($Ru, mpyi($_src_, $Rs))", [],
|
|
"$_src_ = $Rx", M_tc_3x_SLOT23>, ImmRegRel {
|
|
bits<5> Rx;
|
|
bits<5> Ru;
|
|
bits<5> Rs;
|
|
|
|
let IClass = 0b1110;
|
|
|
|
let Inst{27-21} = 0b0011000;
|
|
let Inst{12-8} = Rx;
|
|
let Inst{4-0} = Ru;
|
|
let Inst{20-16} = Rs;
|
|
}
|
|
|
|
|
|
// Vector reduce multiply word by signed half (32x16)
|
|
//Rdd=vrmpyweh(Rss,Rtt)[:<<1]
|
|
def M4_vrmpyeh_s0 : T_M2_vmpy<"vrmpyweh", 0b010, 0b100, 0, 0, 0>;
|
|
def M4_vrmpyeh_s1 : T_M2_vmpy<"vrmpyweh", 0b110, 0b100, 1, 0, 0>;
|
|
|
|
//Rdd=vrmpywoh(Rss,Rtt)[:<<1]
|
|
def M4_vrmpyoh_s0 : T_M2_vmpy<"vrmpywoh", 0b001, 0b010, 0, 0, 0>;
|
|
def M4_vrmpyoh_s1 : T_M2_vmpy<"vrmpywoh", 0b101, 0b010, 1, 0, 0>;
|
|
|
|
//Rdd+=vrmpyweh(Rss,Rtt)[:<<1]
|
|
def M4_vrmpyeh_acc_s0: T_M2_vmpy_acc<"vrmpyweh", 0b001, 0b110, 0, 0>;
|
|
def M4_vrmpyeh_acc_s1: T_M2_vmpy_acc<"vrmpyweh", 0b101, 0b110, 1, 0>;
|
|
|
|
//Rdd=vrmpywoh(Rss,Rtt)[:<<1]
|
|
def M4_vrmpyoh_acc_s0: T_M2_vmpy_acc<"vrmpywoh", 0b011, 0b110, 0, 0>;
|
|
def M4_vrmpyoh_acc_s1: T_M2_vmpy_acc<"vrmpywoh", 0b111, 0b110, 1, 0>;
|
|
|
|
// Vector multiply halfwords, signed by unsigned
|
|
// Rdd=vmpyhsu(Rs,Rt)[:<<]:sat
|
|
def M2_vmpy2su_s0 : T_XTYPE_mpy64 < "vmpyhsu", 0b000, 0b111, 1, 0, 0>;
|
|
def M2_vmpy2su_s1 : T_XTYPE_mpy64 < "vmpyhsu", 0b100, 0b111, 1, 1, 0>;
|
|
|
|
// Rxx+=vmpyhsu(Rs,Rt)[:<<1]:sat
|
|
def M2_vmac2su_s0 : T_XTYPE_mpy64_acc < "vmpyhsu", "+", 0b011, 0b101, 1, 0, 0>;
|
|
def M2_vmac2su_s1 : T_XTYPE_mpy64_acc < "vmpyhsu", "+", 0b111, 0b101, 1, 1, 0>;
|
|
|
|
// Vector polynomial multiply halfwords
|
|
// Rdd=vpmpyh(Rs,Rt)
|
|
def M4_vpmpyh : T_XTYPE_mpy64 < "vpmpyh", 0b110, 0b111, 0, 0, 0>;
|
|
|
|
// Rxx^=vpmpyh(Rs,Rt)
|
|
def M4_vpmpyh_acc : T_XTYPE_mpy64_acc < "vpmpyh", "^", 0b101, 0b111, 0, 0, 0>;
|
|
|
|
// Polynomial multiply words
|
|
// Rdd=pmpyw(Rs,Rt)
|
|
def M4_pmpyw : T_XTYPE_mpy64 < "pmpyw", 0b010, 0b111, 0, 0, 0>;
|
|
|
|
// Rxx^=pmpyw(Rs,Rt)
|
|
def M4_pmpyw_acc : T_XTYPE_mpy64_acc < "pmpyw", "^", 0b001, 0b111, 0, 0, 0>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// XTYPE/MPY -
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// ALU64/Vector compare
|
|
//===----------------------------------------------------------------------===//
|
|
//===----------------------------------------------------------------------===//
|
|
// Template class for vector compare
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
let hasSideEffects = 0 in
|
|
class T_vcmpImm <string Str, bits<2> cmpOp, bits<2> minOp, Operand ImmOprnd>
|
|
: ALU64_rr <(outs PredRegs:$Pd),
|
|
(ins DoubleRegs:$Rss, ImmOprnd:$Imm),
|
|
"$Pd = "#Str#"($Rss, #$Imm)",
|
|
[], "", ALU64_tc_2early_SLOT23> {
|
|
bits<2> Pd;
|
|
bits<5> Rss;
|
|
bits<32> Imm;
|
|
bits<8> ImmBits;
|
|
let ImmBits{6-0} = Imm{6-0};
|
|
let ImmBits{7} = !if (!eq(cmpOp,0b10), 0b0, Imm{7}); // 0 for vcmp[bhw].gtu
|
|
|
|
let IClass = 0b1101;
|
|
|
|
let Inst{27-24} = 0b1100;
|
|
let Inst{22-21} = cmpOp;
|
|
let Inst{20-16} = Rss;
|
|
let Inst{12-5} = ImmBits;
|
|
let Inst{4-3} = minOp;
|
|
let Inst{1-0} = Pd;
|
|
}
|
|
|
|
// Vector compare bytes
|
|
def A4_vcmpbgt : T_vcmp <"vcmpb.gt", 0b1010>;
|
|
|
|
let AsmString = "$Pd = any8(vcmpb.eq($Rss, $Rtt))" in
|
|
def A4_vcmpbeq_any : T_vcmp <"any8(vcmpb.gt", 0b1000>;
|
|
|
|
def A4_vcmpbeqi : T_vcmpImm <"vcmpb.eq", 0b00, 0b00, u8_0Imm>;
|
|
def A4_vcmpbgti : T_vcmpImm <"vcmpb.gt", 0b01, 0b00, s8_0Imm>;
|
|
def A4_vcmpbgtui : T_vcmpImm <"vcmpb.gtu", 0b10, 0b00, u7_0Imm>;
|
|
|
|
// Vector compare halfwords
|
|
def A4_vcmpheqi : T_vcmpImm <"vcmph.eq", 0b00, 0b01, s8_0Imm>;
|
|
def A4_vcmphgti : T_vcmpImm <"vcmph.gt", 0b01, 0b01, s8_0Imm>;
|
|
def A4_vcmphgtui : T_vcmpImm <"vcmph.gtu", 0b10, 0b01, u7_0Imm>;
|
|
|
|
// Vector compare words
|
|
def A4_vcmpweqi : T_vcmpImm <"vcmpw.eq", 0b00, 0b10, s8_0Imm>;
|
|
def A4_vcmpwgti : T_vcmpImm <"vcmpw.gt", 0b01, 0b10, s8_0Imm>;
|
|
def A4_vcmpwgtui : T_vcmpImm <"vcmpw.gtu", 0b10, 0b10, u7_0Imm>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// XTYPE/SHIFT +
|
|
//===----------------------------------------------------------------------===//
|
|
// Shift by immediate and accumulate/logical.
|
|
// Rx=add(#u8,asl(Rx,#U5)) Rx=add(#u8,lsr(Rx,#U5))
|
|
// Rx=sub(#u8,asl(Rx,#U5)) Rx=sub(#u8,lsr(Rx,#U5))
|
|
// Rx=and(#u8,asl(Rx,#U5)) Rx=and(#u8,lsr(Rx,#U5))
|
|
// Rx=or(#u8,asl(Rx,#U5)) Rx=or(#u8,lsr(Rx,#U5))
|
|
let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
|
|
hasNewValue = 1, opNewValue = 0 in
|
|
class T_S4_ShiftOperate<string MnOp, string MnSh, bit asl_lsr,
|
|
bits<2> MajOp, InstrItinClass Itin>
|
|
: MInst_acc<(outs IntRegs:$Rd), (ins u8_0Ext:$u8, IntRegs:$Rx, u5_0Imm:$U5),
|
|
"$Rd = "#MnOp#"(#$u8, "#MnSh#"($Rx, #$U5))",
|
|
[], "$Rd = $Rx", Itin> {
|
|
|
|
bits<5> Rd;
|
|
bits<8> u8;
|
|
bits<5> Rx;
|
|
bits<5> U5;
|
|
|
|
let IClass = 0b1101;
|
|
let Inst{27-24} = 0b1110;
|
|
let Inst{23-21} = u8{7-5};
|
|
let Inst{20-16} = Rd;
|
|
let Inst{13} = u8{4};
|
|
let Inst{12-8} = U5;
|
|
let Inst{7-5} = u8{3-1};
|
|
let Inst{4} = asl_lsr;
|
|
let Inst{3} = u8{0};
|
|
let Inst{2-1} = MajOp;
|
|
}
|
|
|
|
multiclass T_ShiftOperate<string mnemonic, bits<2> MajOp, InstrItinClass Itin> {
|
|
def _asl_ri : T_S4_ShiftOperate<mnemonic, "asl", 0, MajOp, Itin>;
|
|
def _lsr_ri : T_S4_ShiftOperate<mnemonic, "lsr", 1, MajOp, Itin>;
|
|
}
|
|
|
|
defm S4_addi : T_ShiftOperate<"add", 0b10, ALU64_tc_2_SLOT23>;
|
|
defm S4_andi : T_ShiftOperate<"and", 0b00, ALU64_tc_2_SLOT23>;
|
|
defm S4_ori : T_ShiftOperate<"or", 0b01, ALU64_tc_1_SLOT23>;
|
|
defm S4_subi : T_ShiftOperate<"sub", 0b11, ALU64_tc_1_SLOT23>;
|
|
|
|
// Vector conditional negate
|
|
// Rdd=vcnegh(Rss,Rt)
|
|
let Defs = [USR_OVF], Itinerary = S_3op_tc_2_SLOT23 in
|
|
def S2_vcnegh : T_S3op_shiftVect < "vcnegh", 0b11, 0b01>;
|
|
|
|
// Rd=[cround|round](Rs,Rt)
|
|
let hasNewValue = 1, Itinerary = S_3op_tc_2_SLOT23 in {
|
|
def A4_cround_rr : T_S3op_3 < "cround", IntRegs, 0b11, 0b00>;
|
|
def A4_round_rr : T_S3op_3 < "round", IntRegs, 0b11, 0b10>;
|
|
}
|
|
|
|
// Rd=round(Rs,Rt):sat
|
|
let hasNewValue = 1, Defs = [USR_OVF], Itinerary = S_3op_tc_2_SLOT23 in
|
|
def A4_round_rr_sat : T_S3op_3 < "round", IntRegs, 0b11, 0b11, 1>;
|
|
|
|
// Rd=[cmpyiwh|cmpyrwh](Rss,Rt):<<1:rnd:sat
|
|
let Defs = [USR_OVF], Itinerary = S_3op_tc_3x_SLOT23 in {
|
|
def M4_cmpyi_wh : T_S3op_8<"cmpyiwh", 0b100, 1, 1, 1>;
|
|
def M4_cmpyr_wh : T_S3op_8<"cmpyrwh", 0b110, 1, 1, 1>;
|
|
}
|
|
|
|
// Rdd=[add|sub](Rss,Rtt,Px):carry
|
|
let isPredicateLate = 1, hasSideEffects = 0 in
|
|
class T_S3op_carry <string mnemonic, bits<3> MajOp>
|
|
: SInst < (outs DoubleRegs:$Rdd, PredRegs:$Px),
|
|
(ins DoubleRegs:$Rss, DoubleRegs:$Rtt, PredRegs:$Pu),
|
|
"$Rdd = "#mnemonic#"($Rss, $Rtt, $Pu):carry",
|
|
[], "$Px = $Pu", S_3op_tc_1_SLOT23 > {
|
|
bits<5> Rdd;
|
|
bits<5> Rss;
|
|
bits<5> Rtt;
|
|
bits<2> Pu;
|
|
|
|
let IClass = 0b1100;
|
|
|
|
let Inst{27-24} = 0b0010;
|
|
let Inst{23-21} = MajOp;
|
|
let Inst{20-16} = Rss;
|
|
let Inst{12-8} = Rtt;
|
|
let Inst{6-5} = Pu;
|
|
let Inst{4-0} = Rdd;
|
|
}
|
|
|
|
def A4_addp_c : T_S3op_carry < "add", 0b110 >;
|
|
def A4_subp_c : T_S3op_carry < "sub", 0b111 >;
|
|
|
|
let Itinerary = S_3op_tc_3_SLOT23, hasSideEffects = 0 in
|
|
class T_S3op_6 <string mnemonic, bits<3> MinOp, bit isUnsigned>
|
|
: SInst <(outs DoubleRegs:$Rxx),
|
|
(ins DoubleRegs:$dst2, DoubleRegs:$Rss, IntRegs:$Ru),
|
|
"$Rxx = "#mnemonic#"($Rss, $Ru)" ,
|
|
[] , "$dst2 = $Rxx"> {
|
|
bits<5> Rxx;
|
|
bits<5> Rss;
|
|
bits<5> Ru;
|
|
|
|
let IClass = 0b1100;
|
|
|
|
let Inst{27-21} = 0b1011001;
|
|
let Inst{20-16} = Rss;
|
|
let Inst{13} = isUnsigned;
|
|
let Inst{12-8} = Rxx;
|
|
let Inst{7-5} = MinOp;
|
|
let Inst{4-0} = Ru;
|
|
}
|
|
|
|
// Vector reduce maximum halfwords
|
|
// Rxx=vrmax[u]h(Rss,Ru)
|
|
def A4_vrmaxh : T_S3op_6 < "vrmaxh", 0b001, 0>;
|
|
def A4_vrmaxuh : T_S3op_6 < "vrmaxuh", 0b001, 1>;
|
|
|
|
// Vector reduce maximum words
|
|
// Rxx=vrmax[u]w(Rss,Ru)
|
|
def A4_vrmaxw : T_S3op_6 < "vrmaxw", 0b010, 0>;
|
|
def A4_vrmaxuw : T_S3op_6 < "vrmaxuw", 0b010, 1>;
|
|
|
|
// Vector reduce minimum halfwords
|
|
// Rxx=vrmin[u]h(Rss,Ru)
|
|
def A4_vrminh : T_S3op_6 < "vrminh", 0b101, 0>;
|
|
def A4_vrminuh : T_S3op_6 < "vrminuh", 0b101, 1>;
|
|
|
|
// Vector reduce minimum words
|
|
// Rxx=vrmin[u]w(Rss,Ru)
|
|
def A4_vrminw : T_S3op_6 < "vrminw", 0b110, 0>;
|
|
def A4_vrminuw : T_S3op_6 < "vrminuw", 0b110, 1>;
|
|
|
|
// Shift an immediate left by register amount.
|
|
let hasNewValue = 1, hasSideEffects = 0 in
|
|
def S4_lsli: SInst <(outs IntRegs:$Rd), (ins s6_0Imm:$s6, IntRegs:$Rt),
|
|
"$Rd = lsl(#$s6, $Rt)" , [], "", S_3op_tc_1_SLOT23> {
|
|
bits<5> Rd;
|
|
bits<6> s6;
|
|
bits<5> Rt;
|
|
|
|
let IClass = 0b1100;
|
|
|
|
let Inst{27-22} = 0b011010;
|
|
let Inst{20-16} = s6{5-1};
|
|
let Inst{12-8} = Rt;
|
|
let Inst{7-6} = 0b11;
|
|
let Inst{4-0} = Rd;
|
|
let Inst{5} = s6{0};
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// XTYPE/SHIFT -
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// MEMOP
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Template class for MemOp instructions with the register value.
|
|
//===----------------------------------------------------------------------===//
|
|
class MemOp_rr_base <string opc, bits<2> opcBits, Operand ImmOp,
|
|
string memOp, bits<2> memOpBits> :
|
|
MEMInst_V4<(outs),
|
|
(ins IntRegs:$base, ImmOp:$offset, IntRegs:$delta),
|
|
opc#"($base+#$offset)"#memOp#"$delta",
|
|
[]>,
|
|
Requires<[UseMEMOP]> {
|
|
|
|
bits<5> base;
|
|
bits<5> delta;
|
|
bits<32> offset;
|
|
bits<6> offsetBits; // memb - u6:0 , memh - u6:1, memw - u6:2
|
|
|
|
let offsetBits = !if (!eq(opcBits, 0b00), offset{5-0},
|
|
!if (!eq(opcBits, 0b01), offset{6-1},
|
|
!if (!eq(opcBits, 0b10), offset{7-2},0)));
|
|
|
|
let opExtentAlign = opcBits;
|
|
let IClass = 0b0011;
|
|
let Inst{27-24} = 0b1110;
|
|
let Inst{22-21} = opcBits;
|
|
let Inst{20-16} = base;
|
|
let Inst{13} = 0b0;
|
|
let Inst{12-7} = offsetBits;
|
|
let Inst{6-5} = memOpBits;
|
|
let Inst{4-0} = delta;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Template class for MemOp instructions with the immediate value.
|
|
//===----------------------------------------------------------------------===//
|
|
class MemOp_ri_base <string opc, bits<2> opcBits, Operand ImmOp,
|
|
string memOp, bits<2> memOpBits> :
|
|
MEMInst_V4 <(outs),
|
|
(ins IntRegs:$base, ImmOp:$offset, u5_0Imm:$delta),
|
|
opc#"($base+#$offset)"#memOp#"#$delta"
|
|
#!if(memOpBits{1},")", ""), // clrbit, setbit - include ')'
|
|
[]>,
|
|
Requires<[UseMEMOP]> {
|
|
|
|
bits<5> base;
|
|
bits<5> delta;
|
|
bits<32> offset;
|
|
bits<6> offsetBits; // memb - u6:0 , memh - u6:1, memw - u6:2
|
|
|
|
let offsetBits = !if (!eq(opcBits, 0b00), offset{5-0},
|
|
!if (!eq(opcBits, 0b01), offset{6-1},
|
|
!if (!eq(opcBits, 0b10), offset{7-2},0)));
|
|
|
|
let opExtentAlign = opcBits;
|
|
let IClass = 0b0011;
|
|
let Inst{27-24} = 0b1111;
|
|
let Inst{22-21} = opcBits;
|
|
let Inst{20-16} = base;
|
|
let Inst{13} = 0b0;
|
|
let Inst{12-7} = offsetBits;
|
|
let Inst{6-5} = memOpBits;
|
|
let Inst{4-0} = delta;
|
|
}
|
|
|
|
// multiclass to define MemOp instructions with register operand.
|
|
multiclass MemOp_rr<string opc, bits<2> opcBits, Operand ImmOp> {
|
|
def L4_add#NAME : MemOp_rr_base <opc, opcBits, ImmOp, " += ", 0b00>; // add
|
|
def L4_sub#NAME : MemOp_rr_base <opc, opcBits, ImmOp, " -= ", 0b01>; // sub
|
|
def L4_and#NAME : MemOp_rr_base <opc, opcBits, ImmOp, " &= ", 0b10>; // and
|
|
def L4_or#NAME : MemOp_rr_base <opc, opcBits, ImmOp, " |= ", 0b11>; // or
|
|
}
|
|
|
|
// multiclass to define MemOp instructions with immediate Operand.
|
|
multiclass MemOp_ri<string opc, bits<2> opcBits, Operand ImmOp> {
|
|
def L4_iadd#NAME : MemOp_ri_base <opc, opcBits, ImmOp, " += ", 0b00 >;
|
|
def L4_isub#NAME : MemOp_ri_base <opc, opcBits, ImmOp, " -= ", 0b01 >;
|
|
def L4_iand#NAME : MemOp_ri_base<opc, opcBits, ImmOp, " = clrbit(", 0b10>;
|
|
def L4_ior#NAME : MemOp_ri_base<opc, opcBits, ImmOp, " = setbit(", 0b11>;
|
|
}
|
|
|
|
multiclass MemOp_base <string opc, bits<2> opcBits, Operand ImmOp> {
|
|
defm _#NAME : MemOp_rr <opc, opcBits, ImmOp>;
|
|
defm _#NAME : MemOp_ri <opc, opcBits, ImmOp>;
|
|
}
|
|
|
|
// Define MemOp instructions.
|
|
let isExtendable = 1, opExtendable = 1, isExtentSigned = 0 in {
|
|
let opExtentBits = 6, accessSize = ByteAccess in
|
|
defm memopb_io : MemOp_base <"memb", 0b00, u6_0Ext>;
|
|
|
|
let opExtentBits = 7, accessSize = HalfWordAccess in
|
|
defm memoph_io : MemOp_base <"memh", 0b01, u6_1Ext>;
|
|
|
|
let opExtentBits = 8, accessSize = WordAccess in
|
|
defm memopw_io : MemOp_base <"memw", 0b10, u6_2Ext>;
|
|
}
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// XTYPE/PRED +
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Hexagon V4 only supports these flavors of byte/half compare instructions:
|
|
// EQ/GT/GTU. Other flavors like GE/GEU/LT/LTU/LE/LEU are not supported by
|
|
// hardware. However, compiler can still implement these patterns through
|
|
// appropriate patterns combinations based on current implemented patterns.
|
|
// The implemented patterns are: EQ/GT/GTU.
|
|
// Missing patterns are: GE/GEU/LT/LTU/LE/LEU.
|
|
|
|
// Following instruction is not being extended as it results into the
|
|
// incorrect code for negative numbers.
|
|
// Pd=cmpb.eq(Rs,#u8)
|
|
|
|
// p=!cmp.eq(r1,#s10)
|
|
def C4_cmpneqi : T_CMP <"cmp.eq", 0b00, 1, s10_0Ext>;
|
|
def C4_cmpltei : T_CMP <"cmp.gt", 0b01, 1, s10_0Ext>;
|
|
def C4_cmplteui : T_CMP <"cmp.gtu", 0b10, 1, u9_0Ext>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// XTYPE/PRED -
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Multiclass for DeallocReturn
|
|
//===----------------------------------------------------------------------===//
|
|
class L4_RETURN<string mnemonic, bit isNot, bit isPredNew, bit isTak>
|
|
: LD0Inst<(outs), (ins PredRegs:$src),
|
|
!if(isNot, "if (!$src", "if ($src")#
|
|
!if(isPredNew, ".new) ", ") ")#mnemonic#
|
|
!if(isPredNew, #!if(isTak,":t", ":nt"),""),
|
|
[], "", LD_tc_3or4stall_SLOT0> {
|
|
|
|
bits<2> src;
|
|
let BaseOpcode = "L4_RETURN";
|
|
let isPredicatedFalse = isNot;
|
|
let isPredicatedNew = isPredNew;
|
|
let isTaken = isTak;
|
|
let IClass = 0b1001;
|
|
|
|
let Inst{27-16} = 0b011000011110;
|
|
|
|
let Inst{13} = isNot;
|
|
let Inst{12} = isTak;
|
|
let Inst{11} = isPredNew;
|
|
let Inst{10} = 0b0;
|
|
let Inst{9-8} = src;
|
|
let Inst{4-0} = 0b11110;
|
|
}
|
|
|
|
// Produce all predicated forms, p, !p, p.new, !p.new, :t, :nt
|
|
multiclass L4_RETURN_PRED<string mnemonic, bit PredNot> {
|
|
let isPredicated = 1 in {
|
|
def _#NAME# : L4_RETURN <mnemonic, PredNot, 0, 1>;
|
|
def _#NAME#new_pnt : L4_RETURN <mnemonic, PredNot, 1, 0>;
|
|
def _#NAME#new_pt : L4_RETURN <mnemonic, PredNot, 1, 1>;
|
|
}
|
|
}
|
|
|
|
multiclass LD_MISC_L4_RETURN<string mnemonic> {
|
|
let isBarrier = 1, isPredicable = 1 in
|
|
def NAME : LD0Inst <(outs), (ins), mnemonic, [], "",
|
|
LD_tc_3or4stall_SLOT0> {
|
|
let BaseOpcode = "L4_RETURN";
|
|
let IClass = 0b1001;
|
|
let Inst{27-16} = 0b011000011110;
|
|
let Inst{13-10} = 0b0000;
|
|
let Inst{4-0} = 0b11110;
|
|
}
|
|
defm t : L4_RETURN_PRED<mnemonic, 0 >;
|
|
defm f : L4_RETURN_PRED<mnemonic, 1 >;
|
|
}
|
|
|
|
let isReturn = 1, isTerminator = 1,
|
|
Defs = [R29, R30, R31, PC], Uses = [R30], hasSideEffects = 0 in
|
|
defm L4_return: LD_MISC_L4_RETURN <"dealloc_return">, PredNewRel;
|
|
|
|
// Restore registers and dealloc return function call.
|
|
let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1,
|
|
Defs = [R29, R30, R31, PC], isPredicable = 0, isAsmParserOnly = 1 in {
|
|
def RESTORE_DEALLOC_RET_JMP_V4 : T_JMP<"">;
|
|
|
|
let isExtended = 1, opExtendable = 0 in
|
|
def RESTORE_DEALLOC_RET_JMP_V4_EXT : T_JMP<"">;
|
|
|
|
let Defs = [R14, R15, R28, R29, R30, R31, PC] in {
|
|
def RESTORE_DEALLOC_RET_JMP_V4_PIC : T_JMP<"">;
|
|
|
|
let isExtended = 1, opExtendable = 0 in
|
|
def RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC : T_JMP<"">;
|
|
}
|
|
}
|
|
|
|
// Restore registers and dealloc frame before a tail call.
|
|
let isCall = 1, Defs = [R29, R30, R31, PC], isAsmParserOnly = 1 in {
|
|
def RESTORE_DEALLOC_BEFORE_TAILCALL_V4 : T_Call<0, "">, PredRel;
|
|
|
|
let isExtended = 1, opExtendable = 0 in
|
|
def RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT : T_Call<0, "">, PredRel;
|
|
|
|
let Defs = [R14, R15, R28, R29, R30, R31, PC] in {
|
|
def RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC : T_Call<0, "">, PredRel;
|
|
|
|
let isExtended = 1, opExtendable = 0 in
|
|
def RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC : T_Call<0, "">, PredRel;
|
|
}
|
|
}
|
|
|
|
// Save registers function call.
|
|
let isCall = 1, Uses = [R29, R31], isAsmParserOnly = 1 in {
|
|
def SAVE_REGISTERS_CALL_V4 : T_Call<0, "">, PredRel;
|
|
|
|
let isExtended = 1, opExtendable = 0 in
|
|
def SAVE_REGISTERS_CALL_V4_EXT : T_Call<0, "">, PredRel;
|
|
|
|
let Defs = [P0] in
|
|
def SAVE_REGISTERS_CALL_V4STK : T_Call<0, "">, PredRel;
|
|
|
|
let Defs = [P0], isExtended = 1, opExtendable = 0 in
|
|
def SAVE_REGISTERS_CALL_V4STK_EXT : T_Call<0, "">, PredRel;
|
|
|
|
let Defs = [R14, R15, R28] in
|
|
def SAVE_REGISTERS_CALL_V4_PIC : T_Call<0, "">, PredRel;
|
|
|
|
let Defs = [R14, R15, R28], isExtended = 1, opExtendable = 0 in
|
|
def SAVE_REGISTERS_CALL_V4_EXT_PIC : T_Call<0, "">, PredRel;
|
|
|
|
let Defs = [R14, R15, R28, P0] in
|
|
def SAVE_REGISTERS_CALL_V4STK_PIC : T_Call<0, "">, PredRel;
|
|
|
|
let Defs = [R14, R15, R28, P0], isExtended = 1, opExtendable = 0 in
|
|
def SAVE_REGISTERS_CALL_V4STK_EXT_PIC : T_Call<0, "">, PredRel;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Template class for non predicated store instructions with
|
|
// GP-Relative or absolute addressing.
|
|
//===----------------------------------------------------------------------===//
|
|
let hasSideEffects = 0, isPredicable = 1 in
|
|
class T_StoreAbsGP <string mnemonic, RegisterClass RC, Operand ImmOp,
|
|
bits<2>MajOp, bit isAbs, bit isHalf>
|
|
: STInst<(outs), (ins ImmOp:$addr, RC:$src),
|
|
mnemonic # "(#$addr) = $src"#!if(isHalf, ".h",""),
|
|
[], "", V2LDST_tc_st_SLOT01> {
|
|
bits<19> addr;
|
|
bits<5> src;
|
|
bits<16> offsetBits;
|
|
|
|
string ImmOpStr = !cast<string>(ImmOp);
|
|
let offsetBits = !if (!eq(ImmOpStr, "u16_3Imm"), addr{18-3},
|
|
!if (!eq(ImmOpStr, "u16_2Imm"), addr{17-2},
|
|
!if (!eq(ImmOpStr, "u16_1Imm"), addr{16-1},
|
|
/* u16_0Imm */ addr{15-0})));
|
|
// Store upper-half and store doubleword cannot be NV.
|
|
let isNVStorable = !if (!eq(mnemonic, "memd"), 0, !if(isHalf,0,1));
|
|
let Uses = !if (isAbs, [], [GP]);
|
|
|
|
let IClass = 0b0100;
|
|
let Inst{27} = 1;
|
|
let Inst{26-25} = offsetBits{15-14};
|
|
let Inst{24} = 0b0;
|
|
let Inst{23-22} = MajOp;
|
|
let Inst{21} = isHalf;
|
|
let Inst{20-16} = offsetBits{13-9};
|
|
let Inst{13} = offsetBits{8};
|
|
let Inst{12-8} = src;
|
|
let Inst{7-0} = offsetBits{7-0};
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Template class for predicated store instructions with
|
|
// GP-Relative or absolute addressing.
|
|
//===----------------------------------------------------------------------===//
|
|
let hasSideEffects = 0, isPredicated = 1, opExtentBits = 6, opExtendable = 1 in
|
|
class T_StoreAbs_Pred <string mnemonic, RegisterClass RC, bits<2> MajOp,
|
|
bit isHalf, bit isNot, bit isNew>
|
|
: STInst<(outs), (ins PredRegs:$src1, u32_0MustExt:$absaddr, RC: $src2),
|
|
!if(isNot, "if (!$src1", "if ($src1")#!if(isNew, ".new) ",
|
|
") ")#mnemonic#"(#$absaddr) = $src2"#!if(isHalf, ".h",""),
|
|
[], "", ST_tc_st_SLOT01>, AddrModeRel {
|
|
bits<2> src1;
|
|
bits<6> absaddr;
|
|
bits<5> src2;
|
|
|
|
let isPredicatedNew = isNew;
|
|
let isPredicatedFalse = isNot;
|
|
// Store upper-half and store doubleword cannot be NV.
|
|
let isNVStorable = !if (!eq(mnemonic, "memd"), 0, !if(isHalf,0,1));
|
|
|
|
let IClass = 0b1010;
|
|
|
|
let Inst{27-24} = 0b1111;
|
|
let Inst{23-22} = MajOp;
|
|
let Inst{21} = isHalf;
|
|
let Inst{17-16} = absaddr{5-4};
|
|
let Inst{13} = isNew;
|
|
let Inst{12-8} = src2;
|
|
let Inst{7} = 0b1;
|
|
let Inst{6-3} = absaddr{3-0};
|
|
let Inst{2} = isNot;
|
|
let Inst{1-0} = src1;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Template class for predicated store instructions with absolute addressing.
|
|
//===----------------------------------------------------------------------===//
|
|
class T_StoreAbs <string mnemonic, RegisterClass RC, Operand ImmOp,
|
|
bits<2> MajOp, bit isHalf>
|
|
: T_StoreAbsGP <mnemonic, RC, u32_0MustExt, MajOp, 1, isHalf>,
|
|
AddrModeRel {
|
|
string ImmOpStr = !cast<string>(ImmOp);
|
|
let opExtentBits = !if (!eq(ImmOpStr, "u16_3Imm"), 19,
|
|
!if (!eq(ImmOpStr, "u16_2Imm"), 18,
|
|
!if (!eq(ImmOpStr, "u16_1Imm"), 17,
|
|
/* u16_0Imm */ 16)));
|
|
|
|
let opExtentAlign = !if (!eq(ImmOpStr, "u16_3Imm"), 3,
|
|
!if (!eq(ImmOpStr, "u16_2Imm"), 2,
|
|
!if (!eq(ImmOpStr, "u16_1Imm"), 1,
|
|
/* u16_0Imm */ 0)));
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Multiclass for store instructions with absolute addressing.
|
|
//===----------------------------------------------------------------------===//
|
|
let addrMode = Absolute, isExtended = 1 in
|
|
multiclass ST_Abs<string mnemonic, string CextOp, RegisterClass RC,
|
|
Operand ImmOp, bits<2> MajOp, bit isHalf = 0> {
|
|
let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in {
|
|
let opExtendable = 0, isPredicable = 1 in
|
|
def PS_#NAME#abs : T_StoreAbs <mnemonic, RC, ImmOp, MajOp, isHalf>;
|
|
|
|
// Predicated
|
|
def S4_p#NAME#t_abs : T_StoreAbs_Pred<mnemonic, RC, MajOp, isHalf, 0, 0>;
|
|
def S4_p#NAME#f_abs : T_StoreAbs_Pred<mnemonic, RC, MajOp, isHalf, 1, 0>;
|
|
|
|
// .new Predicated
|
|
def S4_p#NAME#tnew_abs : T_StoreAbs_Pred<mnemonic, RC, MajOp, isHalf, 0, 1>;
|
|
def S4_p#NAME#fnew_abs : T_StoreAbs_Pred<mnemonic, RC, MajOp, isHalf, 1, 1>;
|
|
}
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Template class for non predicated new-value store instructions with
|
|
// GP-Relative or absolute addressing.
|
|
//===----------------------------------------------------------------------===//
|
|
let hasSideEffects = 0, isPredicable = 1, mayStore = 1, isNVStore = 1,
|
|
isNewValue = 1, opNewValue = 1 in
|
|
class T_StoreAbsGP_NV <string mnemonic, Operand ImmOp, bits<2>MajOp>
|
|
: NVInst_V4<(outs), (ins ImmOp:$addr, IntRegs:$src),
|
|
mnemonic #"(#$addr) = $src.new",
|
|
[], "", V2LDST_tc_st_SLOT0> {
|
|
bits<19> addr;
|
|
bits<3> src;
|
|
bits<16> offsetBits;
|
|
|
|
string ImmOpStr = !cast<string>(ImmOp);
|
|
let offsetBits = !if (!eq(ImmOpStr, "u16_3Imm"), addr{18-3},
|
|
!if (!eq(ImmOpStr, "u16_2Imm"), addr{17-2},
|
|
!if (!eq(ImmOpStr, "u16_1Imm"), addr{16-1},
|
|
/* u16_0Imm */ addr{15-0})));
|
|
let IClass = 0b0100;
|
|
|
|
let Inst{27} = 1;
|
|
let Inst{26-25} = offsetBits{15-14};
|
|
let Inst{24-21} = 0b0101;
|
|
let Inst{20-16} = offsetBits{13-9};
|
|
let Inst{13} = offsetBits{8};
|
|
let Inst{12-11} = MajOp;
|
|
let Inst{10-8} = src;
|
|
let Inst{7-0} = offsetBits{7-0};
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Template class for predicated new-value store instructions with
|
|
// absolute addressing.
|
|
//===----------------------------------------------------------------------===//
|
|
let hasSideEffects = 0, isPredicated = 1, mayStore = 1, isNVStore = 1,
|
|
isNewValue = 1, opNewValue = 2, opExtentBits = 6, opExtendable = 1 in
|
|
class T_StoreAbs_NV_Pred <string mnemonic, bits<2> MajOp, bit isNot, bit isNew>
|
|
: NVInst_V4<(outs), (ins PredRegs:$src1, u32_0MustExt:$absaddr, IntRegs:$src2),
|
|
!if(isNot, "if (!$src1", "if ($src1")#!if(isNew, ".new) ",
|
|
") ")#mnemonic#"(#$absaddr) = $src2.new",
|
|
[], "", ST_tc_st_SLOT0>, AddrModeRel {
|
|
bits<2> src1;
|
|
bits<6> absaddr;
|
|
bits<3> src2;
|
|
|
|
let isPredicatedNew = isNew;
|
|
let isPredicatedFalse = isNot;
|
|
|
|
let IClass = 0b1010;
|
|
|
|
let Inst{27-24} = 0b1111;
|
|
let Inst{23-21} = 0b101;
|
|
let Inst{17-16} = absaddr{5-4};
|
|
let Inst{13} = isNew;
|
|
let Inst{12-11} = MajOp;
|
|
let Inst{10-8} = src2;
|
|
let Inst{7} = 0b1;
|
|
let Inst{6-3} = absaddr{3-0};
|
|
let Inst{2} = isNot;
|
|
let Inst{1-0} = src1;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Template class for non-predicated new-value store instructions with
|
|
// absolute addressing.
|
|
//===----------------------------------------------------------------------===//
|
|
class T_StoreAbs_NV <string mnemonic, Operand ImmOp, bits<2> MajOp>
|
|
: T_StoreAbsGP_NV <mnemonic, u32_0MustExt, MajOp>, AddrModeRel {
|
|
|
|
string ImmOpStr = !cast<string>(ImmOp);
|
|
let opExtentBits = !if (!eq(ImmOpStr, "u16_3Imm"), 19,
|
|
!if (!eq(ImmOpStr, "u16_2Imm"), 18,
|
|
!if (!eq(ImmOpStr, "u16_1Imm"), 17,
|
|
/* u16_0Imm */ 16)));
|
|
|
|
let opExtentAlign = !if (!eq(ImmOpStr, "u16_3Imm"), 3,
|
|
!if (!eq(ImmOpStr, "u16_2Imm"), 2,
|
|
!if (!eq(ImmOpStr, "u16_1Imm"), 1,
|
|
/* u16_0Imm */ 0)));
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Multiclass for new-value store instructions with absolute addressing.
|
|
//===----------------------------------------------------------------------===//
|
|
let addrMode = Absolute, isExtended = 1 in
|
|
multiclass ST_Abs_NV <string mnemonic, string CextOp, Operand ImmOp,
|
|
bits<2> MajOp> {
|
|
let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in {
|
|
let opExtendable = 0, isPredicable = 1 in
|
|
def PS_#NAME#newabs : T_StoreAbs_NV <mnemonic, ImmOp, MajOp>;
|
|
|
|
// Predicated
|
|
def S4_p#NAME#newt_abs : T_StoreAbs_NV_Pred <mnemonic, MajOp, 0, 0>;
|
|
def S4_p#NAME#newf_abs : T_StoreAbs_NV_Pred <mnemonic, MajOp, 1, 0>;
|
|
|
|
// .new Predicated
|
|
def S4_p#NAME#newtnew_abs : T_StoreAbs_NV_Pred <mnemonic, MajOp, 0, 1>;
|
|
def S4_p#NAME#newfnew_abs : T_StoreAbs_NV_Pred <mnemonic, MajOp, 1, 1>;
|
|
}
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Stores with absolute addressing
|
|
//===----------------------------------------------------------------------===//
|
|
let accessSize = ByteAccess in
|
|
defm storerb : ST_Abs <"memb", "STrib", IntRegs, u16_0Imm, 0b00>,
|
|
ST_Abs_NV <"memb", "STrib", u16_0Imm, 0b00>;
|
|
|
|
let accessSize = HalfWordAccess in
|
|
defm storerh : ST_Abs <"memh", "STrih", IntRegs, u16_1Imm, 0b01>,
|
|
ST_Abs_NV <"memh", "STrih", u16_1Imm, 0b01>;
|
|
|
|
let accessSize = WordAccess in
|
|
defm storeri : ST_Abs <"memw", "STriw", IntRegs, u16_2Imm, 0b10>,
|
|
ST_Abs_NV <"memw", "STriw", u16_2Imm, 0b10>;
|
|
|
|
let isNVStorable = 0, accessSize = DoubleWordAccess in
|
|
defm storerd : ST_Abs <"memd", "STrid", DoubleRegs, u16_3Imm, 0b11>;
|
|
|
|
let isNVStorable = 0, accessSize = HalfWordAccess in
|
|
defm storerf : ST_Abs <"memh", "STrif", IntRegs, u16_1Imm, 0b01, 1>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// GP-relative stores.
|
|
// mem[bhwd](#global)=Rt
|
|
// Once predicated, these instructions map to absolute addressing mode.
|
|
// if ([!]Pv[.new]) mem[bhwd](##global)=Rt
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
let Uses = [GP], isAsmParserOnly = 1 in
|
|
class T_StoreGP <string mnemonic, string BaseOp, RegisterClass RC,
|
|
Operand ImmOp, bits<2> MajOp, bit isHalf = 0>
|
|
: T_StoreAbsGP <mnemonic, RC, ImmOp, MajOp, 0, isHalf> {
|
|
// Set BaseOpcode same as absolute addressing instructions so that
|
|
// non-predicated GP-Rel instructions can have relate with predicated
|
|
// Absolute instruction.
|
|
let BaseOpcode = BaseOp#_abs;
|
|
}
|
|
|
|
let Uses = [GP], isAsmParserOnly = 1 in
|
|
multiclass ST_GP <string mnemonic, string BaseOp, Operand ImmOp,
|
|
bits<2> MajOp, bit isHalf = 0> {
|
|
// Set BaseOpcode same as absolute addressing instructions so that
|
|
// non-predicated GP-Rel instructions can have relate with predicated
|
|
// Absolute instruction.
|
|
let BaseOpcode = BaseOp#_abs in {
|
|
def NAME#gp : T_StoreAbsGP <mnemonic, IntRegs, ImmOp, MajOp,
|
|
0, isHalf>;
|
|
// New-value store
|
|
def NAME#newgp : T_StoreAbsGP_NV <mnemonic, ImmOp, MajOp> ;
|
|
}
|
|
}
|
|
|
|
let accessSize = ByteAccess in
|
|
defm S2_storerb : ST_GP<"memb", "STrib", u16_0Imm, 0b00>, NewValueRel;
|
|
|
|
let accessSize = HalfWordAccess in
|
|
defm S2_storerh : ST_GP<"memh", "STrih", u16_1Imm, 0b01>, NewValueRel;
|
|
|
|
let accessSize = WordAccess in
|
|
defm S2_storeri : ST_GP<"memw", "STriw", u16_2Imm, 0b10>, NewValueRel;
|
|
|
|
let isNVStorable = 0, accessSize = DoubleWordAccess in
|
|
def S2_storerdgp : T_StoreGP <"memd", "STrid", DoubleRegs,
|
|
u16_3Imm, 0b11>, PredNewRel;
|
|
|
|
let isNVStorable = 0, accessSize = HalfWordAccess in
|
|
def S2_storerfgp : T_StoreGP <"memh", "STrif", IntRegs,
|
|
u16_1Imm, 0b01, 1>, PredNewRel;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Template class for non predicated load instructions with
|
|
// absolute addressing mode.
|
|
//===----------------------------------------------------------------------===//
|
|
let isPredicable = 1, hasSideEffects = 0 in
|
|
class T_LoadAbsGP <string mnemonic, RegisterClass RC, Operand ImmOp,
|
|
bits<3> MajOp>
|
|
: LDInst <(outs RC:$dst), (ins ImmOp:$addr),
|
|
"$dst = "#mnemonic# "(#$addr)",
|
|
[], "", V2LDST_tc_ld_SLOT01> {
|
|
bits<5> dst;
|
|
bits<19> addr;
|
|
bits<16> offsetBits;
|
|
|
|
string ImmOpStr = !cast<string>(ImmOp);
|
|
let offsetBits = !if (!eq(ImmOpStr, "u16_3Imm"), addr{18-3},
|
|
!if (!eq(ImmOpStr, "u16_2Imm"), addr{17-2},
|
|
!if (!eq(ImmOpStr, "u16_1Imm"), addr{16-1},
|
|
/* u16_0Imm */ addr{15-0})));
|
|
|
|
let IClass = 0b0100;
|
|
|
|
let Inst{27} = 0b1;
|
|
let Inst{26-25} = offsetBits{15-14};
|
|
let Inst{24} = 0b1;
|
|
let Inst{23-21} = MajOp;
|
|
let Inst{20-16} = offsetBits{13-9};
|
|
let Inst{13-5} = offsetBits{8-0};
|
|
let Inst{4-0} = dst;
|
|
}
|
|
|
|
class T_LoadAbs <string mnemonic, RegisterClass RC, Operand ImmOp,
|
|
bits<3> MajOp>
|
|
: T_LoadAbsGP <mnemonic, RC, u32_0MustExt, MajOp>, AddrModeRel {
|
|
|
|
string ImmOpStr = !cast<string>(ImmOp);
|
|
let opExtentBits = !if (!eq(ImmOpStr, "u16_3Imm"), 19,
|
|
!if (!eq(ImmOpStr, "u16_2Imm"), 18,
|
|
!if (!eq(ImmOpStr, "u16_1Imm"), 17,
|
|
/* u16_0Imm */ 16)));
|
|
|
|
let opExtentAlign = !if (!eq(ImmOpStr, "u16_3Imm"), 3,
|
|
!if (!eq(ImmOpStr, "u16_2Imm"), 2,
|
|
!if (!eq(ImmOpStr, "u16_1Imm"), 1,
|
|
/* u16_0Imm */ 0)));
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Template class for predicated load instructions with
|
|
// absolute addressing mode.
|
|
//===----------------------------------------------------------------------===//
|
|
let isPredicated = 1, hasSideEffects = 0, hasNewValue = 1, opExtentBits = 6,
|
|
opExtendable = 2 in
|
|
class T_LoadAbs_Pred <string mnemonic, RegisterClass RC, bits<3> MajOp,
|
|
bit isPredNot, bit isPredNew>
|
|
: LDInst <(outs RC:$dst), (ins PredRegs:$src1, u32_0MustExt:$absaddr),
|
|
!if(isPredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
|
|
") ")#"$dst = "#mnemonic#"(#$absaddr)">, AddrModeRel {
|
|
bits<5> dst;
|
|
bits<2> src1;
|
|
bits<6> absaddr;
|
|
|
|
let isPredicatedNew = isPredNew;
|
|
let isPredicatedFalse = isPredNot;
|
|
let hasNewValue = !if (!eq(!cast<string>(RC), "DoubleRegs"), 0, 1);
|
|
|
|
let IClass = 0b1001;
|
|
|
|
let Inst{27-24} = 0b1111;
|
|
let Inst{23-21} = MajOp;
|
|
let Inst{20-16} = absaddr{5-1};
|
|
let Inst{13} = 0b1;
|
|
let Inst{12} = isPredNew;
|
|
let Inst{11} = isPredNot;
|
|
let Inst{10-9} = src1;
|
|
let Inst{8} = absaddr{0};
|
|
let Inst{7} = 0b1;
|
|
let Inst{4-0} = dst;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Multiclass for the load instructions with absolute addressing mode.
|
|
//===----------------------------------------------------------------------===//
|
|
multiclass LD_Abs_Pred<string mnemonic, RegisterClass RC, bits<3> MajOp,
|
|
bit PredNot> {
|
|
def _abs : T_LoadAbs_Pred <mnemonic, RC, MajOp, PredNot, 0>;
|
|
// Predicate new
|
|
def new_abs : T_LoadAbs_Pred <mnemonic, RC, MajOp, PredNot, 1>;
|
|
}
|
|
|
|
let addrMode = Absolute, isExtended = 1 in
|
|
multiclass LD_Abs<string mnemonic, string CextOp, RegisterClass RC,
|
|
Operand ImmOp, bits<3> MajOp> {
|
|
let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in {
|
|
let opExtendable = 1, isPredicable = 1 in
|
|
def PS_#NAME#abs: T_LoadAbs <mnemonic, RC, ImmOp, MajOp>;
|
|
|
|
// Predicated
|
|
defm L4_p#NAME#t : LD_Abs_Pred<mnemonic, RC, MajOp, 0>;
|
|
defm L4_p#NAME#f : LD_Abs_Pred<mnemonic, RC, MajOp, 1>;
|
|
}
|
|
}
|
|
|
|
let accessSize = ByteAccess, hasNewValue = 1 in {
|
|
defm loadrb : LD_Abs<"memb", "LDrib", IntRegs, u16_0Imm, 0b000>;
|
|
defm loadrub : LD_Abs<"memub", "LDriub", IntRegs, u16_0Imm, 0b001>;
|
|
}
|
|
|
|
let accessSize = HalfWordAccess, hasNewValue = 1 in {
|
|
defm loadrh : LD_Abs<"memh", "LDrih", IntRegs, u16_1Imm, 0b010>;
|
|
defm loadruh : LD_Abs<"memuh", "LDriuh", IntRegs, u16_1Imm, 0b011>;
|
|
}
|
|
|
|
let accessSize = WordAccess, hasNewValue = 1 in
|
|
defm loadri : LD_Abs<"memw", "LDriw", IntRegs, u16_2Imm, 0b100>;
|
|
|
|
let accessSize = DoubleWordAccess in
|
|
defm loadrd : LD_Abs<"memd", "LDrid", DoubleRegs, u16_3Imm, 0b110>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// multiclass for load instructions with GP-relative addressing mode.
|
|
// Rx=mem[bhwd](##global)
|
|
// Once predicated, these instructions map to absolute addressing mode.
|
|
// if ([!]Pv[.new]) Rx=mem[bhwd](##global)
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
let isAsmParserOnly = 1, Uses = [GP] in
|
|
class T_LoadGP <string mnemonic, string BaseOp, RegisterClass RC, Operand ImmOp,
|
|
bits<3> MajOp>
|
|
: T_LoadAbsGP <mnemonic, RC, ImmOp, MajOp>, PredNewRel {
|
|
let BaseOpcode = BaseOp#_abs;
|
|
}
|
|
|
|
let accessSize = ByteAccess, hasNewValue = 1 in {
|
|
def L2_loadrbgp : T_LoadGP<"memb", "LDrib", IntRegs, u16_0Imm, 0b000>;
|
|
def L2_loadrubgp : T_LoadGP<"memub", "LDriub", IntRegs, u16_0Imm, 0b001>;
|
|
}
|
|
|
|
let accessSize = HalfWordAccess, hasNewValue = 1 in {
|
|
def L2_loadrhgp : T_LoadGP<"memh", "LDrih", IntRegs, u16_1Imm, 0b010>;
|
|
def L2_loadruhgp : T_LoadGP<"memuh", "LDriuh", IntRegs, u16_1Imm, 0b011>;
|
|
}
|
|
|
|
let accessSize = WordAccess, hasNewValue = 1 in
|
|
def L2_loadrigp : T_LoadGP<"memw", "LDriw", IntRegs, u16_2Imm, 0b100>;
|
|
|
|
let accessSize = DoubleWordAccess in
|
|
def L2_loadrdgp : T_LoadGP<"memd", "LDrid", DoubleRegs, u16_3Imm, 0b110>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// :raw for of boundscheck:hi:lo insns
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// A4_boundscheck_lo: Detect if a register is within bounds.
|
|
let hasSideEffects = 0 in
|
|
def A4_boundscheck_lo: ALU64Inst <
|
|
(outs PredRegs:$Pd),
|
|
(ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
|
|
"$Pd = boundscheck($Rss, $Rtt):raw:lo"> {
|
|
bits<2> Pd;
|
|
bits<5> Rss;
|
|
bits<5> Rtt;
|
|
|
|
let IClass = 0b1101;
|
|
|
|
let Inst{27-23} = 0b00100;
|
|
let Inst{13} = 0b1;
|
|
let Inst{7-5} = 0b100;
|
|
let Inst{1-0} = Pd;
|
|
let Inst{20-16} = Rss;
|
|
let Inst{12-8} = Rtt;
|
|
}
|
|
|
|
// A4_boundscheck_hi: Detect if a register is within bounds.
|
|
let hasSideEffects = 0 in
|
|
def A4_boundscheck_hi: ALU64Inst <
|
|
(outs PredRegs:$Pd),
|
|
(ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
|
|
"$Pd = boundscheck($Rss, $Rtt):raw:hi"> {
|
|
bits<2> Pd;
|
|
bits<5> Rss;
|
|
bits<5> Rtt;
|
|
|
|
let IClass = 0b1101;
|
|
|
|
let Inst{27-23} = 0b00100;
|
|
let Inst{13} = 0b1;
|
|
let Inst{7-5} = 0b101;
|
|
let Inst{1-0} = Pd;
|
|
let Inst{20-16} = Rss;
|
|
let Inst{12-8} = Rtt;
|
|
}
|
|
|
|
let hasSideEffects = 0, isAsmParserOnly = 1 in
|
|
def A4_boundscheck : MInst <
|
|
(outs PredRegs:$Pd), (ins IntRegs:$Rs, DoubleRegs:$Rtt),
|
|
"$Pd=boundscheck($Rs,$Rtt)">;
|
|
|
|
// A4_tlbmatch: Detect if a VA/ASID matches a TLB entry.
|
|
let isPredicateLate = 1, hasSideEffects = 0 in
|
|
def A4_tlbmatch : ALU64Inst<(outs PredRegs:$Pd),
|
|
(ins DoubleRegs:$Rs, IntRegs:$Rt),
|
|
"$Pd = tlbmatch($Rs, $Rt)",
|
|
[], "", ALU64_tc_2early_SLOT23> {
|
|
bits<2> Pd;
|
|
bits<5> Rs;
|
|
bits<5> Rt;
|
|
|
|
let IClass = 0b1101;
|
|
let Inst{27-23} = 0b00100;
|
|
let Inst{20-16} = Rs;
|
|
let Inst{13} = 0b1;
|
|
let Inst{12-8} = Rt;
|
|
let Inst{7-5} = 0b011;
|
|
let Inst{1-0} = Pd;
|
|
}
|
|
|
|
// Use LD0Inst for dcfetch, but set "mayLoad" to 0 because this doesn't
|
|
// really do a load.
|
|
let hasSideEffects = 1, mayLoad = 0 in
|
|
def Y2_dcfetchbo : LD0Inst<(outs), (ins IntRegs:$Rs, u11_3Imm:$u11_3),
|
|
"dcfetch($Rs + #$u11_3)",
|
|
[], "", LD_tc_ld_SLOT0> {
|
|
bits<5> Rs;
|
|
bits<14> u11_3;
|
|
|
|
let IClass = 0b1001;
|
|
let Inst{27-21} = 0b0100000;
|
|
let Inst{20-16} = Rs;
|
|
let Inst{13} = 0b0;
|
|
let Inst{10-0} = u11_3{13-3};
|
|
}
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Compound instructions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
let isBranch = 1, hasSideEffects = 0, isExtentSigned = 1,
|
|
isPredicated = 1, isPredicatedNew = 1, isExtendable = 1,
|
|
opExtentBits = 11, opExtentAlign = 2, opExtendable = 1,
|
|
isTerminator = 1 in
|
|
class CJInst_tstbit_R0<string px, bit np, string tnt>
|
|
: InstHexagon<(outs), (ins IntRegs:$Rs, brtarget:$r9_2),
|
|
""#px#" = tstbit($Rs, #0); if ("
|
|
#!if(np, "!","")#""#px#".new) jump:"#tnt#" $r9_2",
|
|
[], "", COMPOUND_CJ_ARCHDEPSLOT, TypeCOMPOUND>, OpcodeHexagon {
|
|
bits<4> Rs;
|
|
bits<11> r9_2;
|
|
|
|
// np: !p[01]
|
|
let isPredicatedFalse = np;
|
|
// tnt: Taken/Not Taken
|
|
let isBrTaken = !if (!eq(tnt, "t"), "true", "false");
|
|
let isTaken = !if (!eq(tnt, "t"), 1, 0);
|
|
|
|
let IClass = 0b0001;
|
|
let Inst{27-26} = 0b00;
|
|
let Inst{25} = !if (!eq(px, "!p1"), 1,
|
|
!if (!eq(px, "p1"), 1, 0));
|
|
let Inst{24-23} = 0b11;
|
|
let Inst{22} = np;
|
|
let Inst{21-20} = r9_2{10-9};
|
|
let Inst{19-16} = Rs;
|
|
let Inst{13} = !if (!eq(tnt, "t"), 1, 0);
|
|
let Inst{9-8} = 0b11;
|
|
let Inst{7-1} = r9_2{8-2};
|
|
}
|
|
|
|
let Defs = [PC, P0], Uses = [P0] in {
|
|
def J4_tstbit0_tp0_jump_nt : CJInst_tstbit_R0<"p0", 0, "nt">;
|
|
def J4_tstbit0_tp0_jump_t : CJInst_tstbit_R0<"p0", 0, "t">;
|
|
def J4_tstbit0_fp0_jump_nt : CJInst_tstbit_R0<"p0", 1, "nt">;
|
|
def J4_tstbit0_fp0_jump_t : CJInst_tstbit_R0<"p0", 1, "t">;
|
|
}
|
|
|
|
let Defs = [PC, P1], Uses = [P1] in {
|
|
def J4_tstbit0_tp1_jump_nt : CJInst_tstbit_R0<"p1", 0, "nt">;
|
|
def J4_tstbit0_tp1_jump_t : CJInst_tstbit_R0<"p1", 0, "t">;
|
|
def J4_tstbit0_fp1_jump_nt : CJInst_tstbit_R0<"p1", 1, "nt">;
|
|
def J4_tstbit0_fp1_jump_t : CJInst_tstbit_R0<"p1", 1, "t">;
|
|
}
|
|
|
|
|
|
let isBranch = 1, hasSideEffects = 0,
|
|
isExtentSigned = 1, isPredicated = 1, isPredicatedNew = 1,
|
|
isExtendable = 1, opExtentBits = 11, opExtentAlign = 2,
|
|
opExtendable = 2, isTerminator = 1 in
|
|
class CJInst_RR<string px, string op, bit np, string tnt>
|
|
: InstHexagon<(outs), (ins IntRegs:$Rs, IntRegs:$Rt, brtarget:$r9_2),
|
|
""#px#" = cmp."#op#"($Rs, $Rt); if ("
|
|
#!if(np, "!","")#""#px#".new) jump:"#tnt#" $r9_2",
|
|
[], "", COMPOUND_CJ_ARCHDEPSLOT, TypeCOMPOUND>, OpcodeHexagon {
|
|
bits<4> Rs;
|
|
bits<4> Rt;
|
|
bits<11> r9_2;
|
|
|
|
// np: !p[01]
|
|
let isPredicatedFalse = np;
|
|
// tnt: Taken/Not Taken
|
|
let isBrTaken = !if (!eq(tnt, "t"), "true", "false");
|
|
let isTaken = !if (!eq(tnt, "t"), 1, 0);
|
|
|
|
let IClass = 0b0001;
|
|
let Inst{27-23} = !if (!eq(op, "eq"), 0b01000,
|
|
!if (!eq(op, "gt"), 0b01001,
|
|
!if (!eq(op, "gtu"), 0b01010, 0)));
|
|
let Inst{22} = np;
|
|
let Inst{21-20} = r9_2{10-9};
|
|
let Inst{19-16} = Rs;
|
|
let Inst{13} = !if (!eq(tnt, "t"), 1, 0);
|
|
// px: Predicate reg 0/1
|
|
let Inst{12} = !if (!eq(px, "!p1"), 1,
|
|
!if (!eq(px, "p1"), 1, 0));
|
|
let Inst{11-8} = Rt;
|
|
let Inst{7-1} = r9_2{8-2};
|
|
}
|
|
|
|
// P[10] taken/not taken.
|
|
multiclass T_tnt_CJInst_RR<string op, bit np> {
|
|
let Defs = [PC, P0], Uses = [P0] in {
|
|
def NAME#p0_jump_nt : CJInst_RR<"p0", op, np, "nt">;
|
|
def NAME#p0_jump_t : CJInst_RR<"p0", op, np, "t">;
|
|
}
|
|
let Defs = [PC, P1], Uses = [P1] in {
|
|
def NAME#p1_jump_nt : CJInst_RR<"p1", op, np, "nt">;
|
|
def NAME#p1_jump_t : CJInst_RR<"p1", op, np, "t">;
|
|
}
|
|
}
|
|
// Predicate / !Predicate
|
|
multiclass T_pnp_CJInst_RR<string op>{
|
|
defm J4_cmp#NAME#_t : T_tnt_CJInst_RR<op, 0>;
|
|
defm J4_cmp#NAME#_f : T_tnt_CJInst_RR<op, 1>;
|
|
}
|
|
// TypeCJ Instructions compare RR and jump
|
|
defm eq : T_pnp_CJInst_RR<"eq">;
|
|
defm gt : T_pnp_CJInst_RR<"gt">;
|
|
defm gtu : T_pnp_CJInst_RR<"gtu">;
|
|
|
|
let isBranch = 1, hasSideEffects = 0, isExtentSigned = 1,
|
|
isPredicated = 1, isPredicatedNew = 1, isExtendable = 1, opExtentBits = 11,
|
|
opExtentAlign = 2, opExtendable = 2, isTerminator = 1 in
|
|
class CJInst_RU5<string px, string op, bit np, string tnt>
|
|
: InstHexagon<(outs), (ins IntRegs:$Rs, u5_0Imm:$U5, brtarget:$r9_2),
|
|
""#px#" = cmp."#op#"($Rs, #$U5); if ("
|
|
#!if(np, "!","")#""#px#".new) jump:"#tnt#" $r9_2",
|
|
[], "", COMPOUND_CJ_ARCHDEPSLOT, TypeCOMPOUND>, OpcodeHexagon {
|
|
bits<4> Rs;
|
|
bits<5> U5;
|
|
bits<11> r9_2;
|
|
|
|
// np: !p[01]
|
|
let isPredicatedFalse = np;
|
|
// tnt: Taken/Not Taken
|
|
let isBrTaken = !if (!eq(tnt, "t"), "true", "false");
|
|
let isTaken = !if (!eq(tnt, "t"), 1, 0);
|
|
|
|
let IClass = 0b0001;
|
|
let Inst{27-26} = 0b00;
|
|
// px: Predicate reg 0/1
|
|
let Inst{25} = !if (!eq(px, "!p1"), 1,
|
|
!if (!eq(px, "p1"), 1, 0));
|
|
let Inst{24-23} = !if (!eq(op, "eq"), 0b00,
|
|
!if (!eq(op, "gt"), 0b01,
|
|
!if (!eq(op, "gtu"), 0b10, 0)));
|
|
let Inst{22} = np;
|
|
let Inst{21-20} = r9_2{10-9};
|
|
let Inst{19-16} = Rs;
|
|
let Inst{13} = !if (!eq(tnt, "t"), 1, 0);
|
|
let Inst{12-8} = U5;
|
|
let Inst{7-1} = r9_2{8-2};
|
|
}
|
|
// P[10] taken/not taken.
|
|
multiclass T_tnt_CJInst_RU5<string op, bit np> {
|
|
let Defs = [PC, P0], Uses = [P0] in {
|
|
def NAME#p0_jump_nt : CJInst_RU5<"p0", op, np, "nt">;
|
|
def NAME#p0_jump_t : CJInst_RU5<"p0", op, np, "t">;
|
|
}
|
|
let Defs = [PC, P1], Uses = [P1] in {
|
|
def NAME#p1_jump_nt : CJInst_RU5<"p1", op, np, "nt">;
|
|
def NAME#p1_jump_t : CJInst_RU5<"p1", op, np, "t">;
|
|
}
|
|
}
|
|
// Predicate / !Predicate
|
|
multiclass T_pnp_CJInst_RU5<string op>{
|
|
defm J4_cmp#NAME#i_t : T_tnt_CJInst_RU5<op, 0>;
|
|
defm J4_cmp#NAME#i_f : T_tnt_CJInst_RU5<op, 1>;
|
|
}
|
|
// TypeCJ Instructions compare RI and jump
|
|
defm eq : T_pnp_CJInst_RU5<"eq">;
|
|
defm gt : T_pnp_CJInst_RU5<"gt">;
|
|
defm gtu : T_pnp_CJInst_RU5<"gtu">;
|
|
|
|
let isBranch = 1, hasSideEffects = 0, isExtentSigned = 1,
|
|
isPredicated = 1, isPredicatedFalse = 1, isPredicatedNew = 1,
|
|
isExtendable = 1, opExtentBits = 11, opExtentAlign = 2, opExtendable = 1,
|
|
isTerminator = 1 in
|
|
class CJInst_Rn1<string px, string op, bit np, string tnt>
|
|
: InstHexagon<(outs), (ins IntRegs:$Rs, brtarget:$r9_2),
|
|
""#px#" = cmp."#op#"($Rs,#-1); if ("
|
|
#!if(np, "!","")#""#px#".new) jump:"#tnt#" $r9_2",
|
|
[], "", COMPOUND_CJ_ARCHDEPSLOT, TypeCOMPOUND>, OpcodeHexagon {
|
|
bits<4> Rs;
|
|
bits<11> r9_2;
|
|
|
|
// np: !p[01]
|
|
let isPredicatedFalse = np;
|
|
// tnt: Taken/Not Taken
|
|
let isBrTaken = !if (!eq(tnt, "t"), "true", "false");
|
|
let isTaken = !if (!eq(tnt, "t"), 1, 0);
|
|
|
|
let IClass = 0b0001;
|
|
let Inst{27-26} = 0b00;
|
|
let Inst{25} = !if (!eq(px, "!p1"), 1,
|
|
!if (!eq(px, "p1"), 1, 0));
|
|
|
|
let Inst{24-23} = 0b11;
|
|
let Inst{22} = np;
|
|
let Inst{21-20} = r9_2{10-9};
|
|
let Inst{19-16} = Rs;
|
|
let Inst{13} = !if (!eq(tnt, "t"), 1, 0);
|
|
let Inst{9-8} = !if (!eq(op, "eq"), 0b00,
|
|
!if (!eq(op, "gt"), 0b01, 0));
|
|
let Inst{7-1} = r9_2{8-2};
|
|
}
|
|
|
|
// P[10] taken/not taken.
|
|
multiclass T_tnt_CJInst_Rn1<string op, bit np> {
|
|
let Defs = [PC, P0], Uses = [P0] in {
|
|
def NAME#p0_jump_nt : CJInst_Rn1<"p0", op, np, "nt">;
|
|
def NAME#p0_jump_t : CJInst_Rn1<"p0", op, np, "t">;
|
|
}
|
|
let Defs = [PC, P1], Uses = [P1] in {
|
|
def NAME#p1_jump_nt : CJInst_Rn1<"p1", op, np, "nt">;
|
|
def NAME#p1_jump_t : CJInst_Rn1<"p1", op, np, "t">;
|
|
}
|
|
}
|
|
// Predicate / !Predicate
|
|
multiclass T_pnp_CJInst_Rn1<string op>{
|
|
defm J4_cmp#NAME#n1_t : T_tnt_CJInst_Rn1<op, 0>;
|
|
defm J4_cmp#NAME#n1_f : T_tnt_CJInst_Rn1<op, 1>;
|
|
}
|
|
// TypeCJ Instructions compare -1 and jump
|
|
defm eq : T_pnp_CJInst_Rn1<"eq">;
|
|
defm gt : T_pnp_CJInst_Rn1<"gt">;
|
|
|
|
// J4_jumpseti: Direct unconditional jump and set register to immediate.
|
|
let Defs = [PC], isBranch = 1, hasSideEffects = 0, hasNewValue = 1,
|
|
isExtentSigned = 1, opNewValue = 0, isExtendable = 1, opExtentBits = 11,
|
|
opExtentAlign = 2, opExtendable = 2 in
|
|
def J4_jumpseti: CJInst_JMPSET <
|
|
(outs IntRegs:$Rd),
|
|
(ins u6_0Imm:$U6, brtarget:$r9_2),
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|
"$Rd = #$U6 ; jump $r9_2"> {
|
|
bits<4> Rd;
|
|
bits<6> U6;
|
|
bits<11> r9_2;
|
|
|
|
let IClass = 0b0001;
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|
let Inst{27-24} = 0b0110;
|
|
let Inst{21-20} = r9_2{10-9};
|
|
let Inst{19-16} = Rd;
|
|
let Inst{13-8} = U6;
|
|
let Inst{7-1} = r9_2{8-2};
|
|
}
|
|
|
|
// J4_jumpsetr: Direct unconditional jump and transfer register.
|
|
let Defs = [PC], isBranch = 1, hasSideEffects = 0, hasNewValue = 1,
|
|
isExtentSigned = 1, opNewValue = 0, isExtendable = 1, opExtentBits = 11,
|
|
opExtentAlign = 2, opExtendable = 2 in
|
|
def J4_jumpsetr: CJInst_JMPSET <
|
|
(outs IntRegs:$Rd),
|
|
(ins IntRegs:$Rs, brtarget:$r9_2),
|
|
"$Rd = $Rs ; jump $r9_2"> {
|
|
bits<4> Rd;
|
|
bits<4> Rs;
|
|
bits<11> r9_2;
|
|
|
|
let IClass = 0b0001;
|
|
let Inst{27-24} = 0b0111;
|
|
let Inst{21-20} = r9_2{10-9};
|
|
let Inst{11-8} = Rd;
|
|
let Inst{19-16} = Rs;
|
|
let Inst{7-1} = r9_2{8-2};
|
|
}
|
|
|
|
// Duplex instructions
|
|
//===----------------------------------------------------------------------===//
|
|
include "HexagonIsetDx.td"
|