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llvm-mirror/test/CodeGen
Jessica Clarke 8c42ad8897 [SelectionDAG][Mips][PowerPC][RISCV][WebAssembly] Teach computeKnownBits/ComputeNumSignBits about atomics
Unlike normal loads these don't have an extension field, but we know
from TargetLowering whether these are sign-extending or zero-extending,
and so can optimise away unnecessary extensions.

This was noticed on RISC-V, where sign extensions in the calling
convention would result in unnecessary explicit extension instructions,
but this also fixes some Mips inefficiencies. PowerPC sees churn in the
tests as all the zero extensions are only for promoting 32-bit to
64-bit, but these zero extensions are still not optimised away as they
should be, likely due to i32 being a legal type.

This also simplifies the WebAssembly code somewhat, which currently
works around the lack of target-independent combines with some ugly
patterns that break once they're optimised away.

Re-landed with correct handling in ComputeNumSignBits for Tmp == VTBits,
where zero-extending atomics were incorrectly returning 0 rather than
the (slightly confusing) required return value of 1.

Re-landed again after D102819 fixed PowerPC to correctly zero-extend all
of its atomics as it claimed to do, since the combination of that bug
and this optimisation caused buildbot regressions.

Reviewed By: RKSimon, atanasyan

Differential Revision: https://reviews.llvm.org/D101342
2021-05-20 20:34:23 +01:00
..
AArch64 Revert "[Remarks] Add analysis remarks for memset/memcpy/memmove lengths" 2021-05-20 12:19:16 -07:00
AMDGPU Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" 2021-05-19 09:29:19 -07:00
ARC
ARM [ARM][AArch64] SLSHardening: make non-comdat thunks possible 2021-05-20 17:07:05 +02:00
AVR
BPF
Generic
Hexagon
Inputs
Lanai
M68k
Mips [SelectionDAG][Mips][PowerPC][RISCV][WebAssembly] Teach computeKnownBits/ComputeNumSignBits about atomics 2021-05-20 20:34:23 +01:00
MIR
MSP430
NVPTX
PowerPC [SelectionDAG][Mips][PowerPC][RISCV][WebAssembly] Teach computeKnownBits/ComputeNumSignBits about atomics 2021-05-20 20:34:23 +01:00
RISCV [SelectionDAG][Mips][PowerPC][RISCV][WebAssembly] Teach computeKnownBits/ComputeNumSignBits about atomics 2021-05-20 20:34:23 +01:00
SPARC [TargetLowering] Only inspect attributes in the arguments for ArgListEntry 2021-05-18 14:30:22 -07:00
SystemZ [TargetLowering] Only inspect attributes in the arguments for ArgListEntry 2021-05-18 14:30:22 -07:00
Thumb
Thumb2 [ARM] Extra tests for MVE vhadd and vmulh. NFC 2021-05-20 14:13:39 +01:00
VE
WebAssembly [WebAssembly] Ignore filters in Emscripten EH landingpads 2021-05-20 01:28:16 -07:00
WinCFGuard
WinEH
X86 [X86][AVX] Don't scrub pointer math in avx-vperm2x128.ll 2021-05-20 10:53:20 +01:00
XCore