David Green 0d22518864 [ARM] Extra tests for MVE vhadd and vmulh. NFC		2021-05-20 14:13:39 +01:00
..
LowOverheadLoops	[ARM] Expand predecessor search to multiple blocks when reverting WhileLoopStarts	2021-05-14 15:08:14 +01:00
mve-intrinsics
2009-07-17-CrossRegClassCopy.ll
2009-07-21-ISelBug.ll
2009-07-23-CPIslandBug.ll
2009-07-30-PEICrash.ll
2009-08-01-WrongLDRBOpc.ll
2009-08-02-CoalescerBug.ll
2009-08-04-CoalescerAssert.ll
2009-08-04-CoalescerBug.ll
2009-08-04-ScavengerAssert.ll
2009-08-04-SubregLoweringBug2.ll
2009-08-04-SubregLoweringBug3.ll
2009-08-04-SubregLoweringBug.ll
2009-08-06-SpDecBug.ll
2009-08-07-CoalescerBug.ll
2009-08-07-NeonFPBug.ll
2009-08-08-ScavengerAssert.ll
2009-08-10-ISelBug.ll
2009-08-21-PostRAKill4.ll
2009-09-01-PostRAProlog.ll
2009-10-15-ITBlockBranch.ll
2009-11-01-CopyReg2RegBug.ll
2009-11-11-ScavengerAssert.ll
2009-11-13-STRDBug.ll
2009-12-01-LoopIVUsers.ll
2010-01-06-TailDuplicateLabels.ll
2010-01-19-RemovePredicates.ll
2010-02-11-phi-cycle.ll	[CPG][ARM] Optimize towards branch on zero in codegenprepare	2021-05-16 17:54:06 +01:00
2010-02-24-BigStack.ll
2010-03-08-addi12-ccout.ll
2010-03-15-AsmCCClobber.ll
2010-04-15-DynAllocBug.ll
2010-04-26-CopyRegCrash.ll
2010-05-24-rsbs.ll
2010-06-14-NEONCoalescer.ll
2010-06-19-ITBlockCrash.ll
2010-06-21-TailMergeBug.ll
2010-08-10-VarSizedAllocaBug.ll
2010-11-22-EpilogueBug.ll
2010-12-03-AddSPNarrowing.ll
2011-04-21-FILoweringBug.ll
2011-06-07-TwoAddrEarlyClobber.ll
2011-12-16-T2SizeReduceAssert.ll
2012-01-13-CBNZBug.ll
2013-02-19-tail-call-register-hint.ll
2013-03-02-vduplane-nonconstant-source-index.ll
2013-03-06-vector-sext-operand-scalarize.ll
aapcs.ll
active_lane_mask.ll	[ARM] Create VMOVRRD from adjacent vector extracts	2021-04-20 15:15:43 +01:00
aligned-constants.ll
aligned-nonfallthrough.ll	[ARM] Remove DLS lr, lr	2021-02-02 11:09:31 +00:00
aligned-spill.ll
bfi.ll
bfx.ll
bicbfi.ll
block-placement.mir	[ARM] Simplification to ARMBlockPlacement Pass.	2021-05-06 01:20:18 +01:00
bug-subw.ll
buildvector-crash.ll
call-site-info-update.ll
carry.ll
cbnz.ll
cde-gpr.ll
cde-vec.ll
cde-vfp.ll
cmp-frame.ll
constant-hoisting.ll
constant-islands-cbz.ll
constant-islands-cbz.mir	[ARM] Ensure undef is propagated to CBZ/CBNZ flags	2021-03-03 08:02:58 +00:00
constant-islands-cbzundef.mir	[ARM] Ensure undef is propagated to CBZ/CBNZ flags	2021-03-03 08:02:58 +00:00
constant-islands-jump-table.ll
constant-islands-ldrsb.mir	[ARM] Add handling of t2LDRSB/t2LDRSH in Constant Island Pass	2021-03-02 08:46:07 +00:00
constant-islands-new-island-padding.ll
constant-islands-new-island.ll
constant-islands.ll
cortex-fp.ll
crash.ll
cross-rc-coalescing-1.ll
cross-rc-coalescing-2.ll
csel.ll	[ARM] Ensure CSINC has one use in CSINV combine	2021-04-29 10:59:14 +01:00
div.ll
emit-unwinding.ll
fir.ll
float-cmp.ll
float-intrinsics-double.ll
float-intrinsics-float.ll
float-ops.ll
fp16-stacksplot.mir
frame-index-addrmode-t2i8s4.mir
frame-pointer.ll
frameless2.ll
frameless.ll
high-reg-spill.mir
ifcvt-cbz.mir
ifcvt-compare.ll
ifcvt-dead-predicate.mir
ifcvt-minsize.ll
ifcvt-neon-deprecated.mir
ifcvt-no-branch-predictor.ll
ifcvt-rescan-bug-2016-08-22.ll
ifcvt-rescan-diamonds.ll
inflate-regs.ll
inline-asm-i-constraint-i1.ll
inlineasm-error-t-toofewregs-mve.ll
inlineasm-mve.ll
inlineasm.ll
intrinsics-cc.ll
intrinsics-coprocessor.ll
large-call.ll
large-stack.ll
ldr-str-imm12.ll
lit.local.cfg
longMACt.ll
lsll0.ll
lsr-deficiency.ll
m4-sched-ldr.mir
m4-sched-regs.ll
machine-licm.ll
mul_const.ll
mve-abs.ll	[ARM] Create VMOVRRD from adjacent vector extracts	2021-04-20 15:15:43 +01:00
mve-basic.ll
mve-be.ll	[ARM] VECTOR_REG_CAST undef -> undef	2021-02-28 11:13:49 +00:00
mve-bitarith.ll
mve-bitcasts.ll
mve-bitreverse.ll
mve-blockplacement.ll	[ARM] Remove dead mov's in preheader of tail predicated loops	2021-02-11 10:48:20 +00:00
mve-bswap.ll
mve-ctlz.ll	[ARM] Create VMOVRRD from adjacent vector extracts	2021-04-20 15:15:43 +01:00
mve-ctpop.ll	[ARM] Create VMOVRRD from adjacent vector extracts	2021-04-20 15:15:43 +01:00
mve-cttz.ll	[ARM] Create VMOVRRD from adjacent vector extracts	2021-04-20 15:15:43 +01:00
mve-div-expand.ll	[ARM] Create VMOVRRD from adjacent vector extracts	2021-04-20 15:15:43 +01:00
mve-extractelt.ll
mve-extractstore.ll	[ARM] Optimize fp store of extract to integer store if already available.	2021-02-12 18:34:58 +00:00
mve-float16regloops.ll	[ARM] Simplification to ARMBlockPlacement Pass.	2021-05-06 01:20:18 +01:00
mve-float32regloops.ll	[ARM] Constrain CMPZ shift combine to a single use	2021-05-13 18:31:01 +01:00
mve-fma-loops.ll
mve-fmas.ll	[ARM] KnownBits for CSINC/CSNEG/CSINV	2021-03-04 08:40:20 +00:00
mve-fmath.ll	[ARM] Create VMOVRRD from adjacent vector extracts	2021-04-20 15:15:43 +01:00
mve-fp16convertloops.ll	[ARM] Add FP handling for MVE lane interleaving	2021-04-12 15:28:13 +01:00
mve-fp-negabs.ll	[ARM] Select VINS from vector inserts	2021-02-02 13:50:02 +00:00
mve-frint.ll	[ARM] Select VINS from vector inserts	2021-02-02 13:50:02 +00:00
mve-gather-increment.ll	[ARM] Create VMOVRRD from adjacent vector extracts	2021-04-20 15:15:43 +01:00
mve-gather-ind8-unscaled.ll	[ARM] Create VMOVRRD from adjacent vector extracts	2021-04-20 15:15:43 +01:00
mve-gather-ind16-scaled.ll	[ARM] Create VMOVRRD from adjacent vector extracts	2021-04-20 15:15:43 +01:00
mve-gather-ind16-unscaled.ll	[ARM] Create VMOVRRD from adjacent vector extracts	2021-04-20 15:15:43 +01:00
mve-gather-ind32-scaled.ll
mve-gather-ind32-unscaled.ll	[ARM] Create VMOVRRD from adjacent vector extracts	2021-04-20 15:15:43 +01:00
mve-gather-optimisation-deep.ll
mve-gather-ptrs.ll	[ARM] Create VMOVRRD from adjacent vector extracts	2021-04-20 15:15:43 +01:00
mve-gather-scatter-opt.ll	[ARM] Create VMOVRRD from adjacent vector extracts	2021-04-20 15:15:43 +01:00
mve-gather-scatter-optimisation.ll	[ARM] Transforming memset to Tail predicated Loop	2021-05-07 13:35:53 +01:00
mve-gather-scatter-ptr-address.ll	[ARM] Remove DLS lr, lr	2021-02-02 11:09:31 +00:00
mve-gather-scatter-tailpred.ll	[ARM] Move t2DoLoopStart reg alloc hint	2021-03-11 17:56:19 +00:00
mve-gather-tailpred.ll	[ARM] Don't handle low overhead branches in AnalyzeBranch	2021-01-18 17:16:07 +00:00
mve-gatherscatter-mmo.ll	[ARM] Memory operands for MVE gathers/scatters	2021-05-03 11:24:59 +01:00
mve-halving.ll
mve-laneinterleaving-cost.ll	[ARM] Create VMOVRRD from adjacent vector extracts	2021-04-20 15:15:43 +01:00
mve-laneinterleaving.ll	[ARM] Create VMOVRRD from adjacent vector extracts	2021-04-20 15:15:43 +01:00
mve-ldst-offset.ll
mve-ldst-postinc.ll
mve-ldst-preinc.ll
mve-ldst-regimm.ll
mve-loadstore.ll
mve-masked-ldst-offset.ll
mve-masked-ldst-postinc.ll
mve-masked-ldst-preinc.ll
mve-masked-ldst.ll	[ARM] Move double vector insert patterns using vins to DAG combine	2021-02-22 09:29:47 +00:00
mve-masked-load.ll	[ARM] Create VMOVRRD from adjacent vector extracts	2021-04-20 15:15:43 +01:00
mve-masked-store.ll	[ARM] Create VMOVRRD from adjacent vector extracts	2021-04-20 15:15:43 +01:00
mve-memtp-loop.ll	[ARM] Add an extra memset test showing reverted WLSTP loops. NFC	2021-05-15 16:48:58 +01:00
mve-minmax.ll	[ARM] Create VMOVRRD from adjacent vector extracts	2021-04-20 15:15:43 +01:00
mve-multivec-spill.ll	[ARM] Transfer memory operands for VLDn	2021-05-03 00:04:21 +01:00
mve-neg.ll	[ARM] Create VMOVRRD from adjacent vector extracts	2021-04-20 15:15:43 +01:00
mve-nofloat.ll	[ARM] Create VMOVRRD from adjacent vector extracts	2021-04-20 15:15:43 +01:00
mve-nounrolledremainder.ll	[ARM] KnownBits for CSINC/CSNEG/CSINV	2021-03-04 08:40:20 +00:00
mve-phireg.ll	[ARM] Transforming memset to Tail predicated Loop	2021-05-07 13:35:53 +01:00
mve-postinc-dct.ll	[ARM] Remove dead mov's in preheader of tail predicated loops	2021-02-11 10:48:20 +00:00
mve-postinc-distribute.ll	[ARM] Improve WLS lowering	2021-03-11 17:56:19 +00:00
mve-postinc-distribute.mir	[ARM] Use rGPR for writeback vldrs	2021-02-16 16:44:47 +00:00
mve-postinc-lsr.ll	[ARM] Constrain CMPZ shift combine to a single use	2021-05-13 18:31:01 +01:00
mve-pred-and.ll	[ARM] Create VMOVRRD from adjacent vector extracts	2021-04-20 15:15:43 +01:00
mve-pred-bitcast.ll	[ARM] Create VMOVRRD from adjacent vector extracts	2021-04-20 15:15:43 +01:00
mve-pred-build-const.ll
mve-pred-build-var.ll	[ARM] Combine sub 0, csinc X, Y, CC -> csinv -X, Y, CC	2021-04-16 11:52:31 +01:00
mve-pred-const.ll
mve-pred-constfold.ll
mve-pred-convert.ll
mve-pred-ext.ll	[ARM] Create VMOVRRD from adjacent vector extracts	2021-04-20 15:15:43 +01:00
mve-pred-loadstore.ll	[ARM] Create VMOVRRD from adjacent vector extracts	2021-04-20 15:15:43 +01:00
mve-pred-not.ll	[ARM] Create VMOVRRD from adjacent vector extracts	2021-04-20 15:15:43 +01:00
mve-pred-or.ll	[ARM] Create VMOVRRD from adjacent vector extracts	2021-04-20 15:15:43 +01:00
mve-pred-selectop2.ll
mve-pred-selectop3.ll
mve-pred-selectop.ll
mve-pred-shuffle.ll	[ARM] Create VMOVRRD from adjacent vector extracts	2021-04-20 15:15:43 +01:00
mve-pred-spill.ll
mve-pred-threshold.ll	[ARM] Remove DLS lr, lr	2021-02-02 11:09:31 +00:00
mve-pred-vctpvpsel.ll	[ARM] Move t2DoLoopStart reg alloc hint	2021-03-11 17:56:19 +00:00
mve-pred-vselect.ll	[ARM] Create VMOVRRD from adjacent vector extracts	2021-04-20 15:15:43 +01:00
mve-pred-xor.ll	[ARM] Create VMOVRRD from adjacent vector extracts	2021-04-20 15:15:43 +01:00
mve-qrintr.ll
mve-satmul-loops.ll	[ARM] Create VMOVRRD from adjacent vector extracts	2021-04-20 15:15:43 +01:00
mve-saturating-arith.ll	[ARM] Create VMOVRRD from adjacent vector extracts	2021-04-20 15:15:43 +01:00
mve-scatter-increment.ll	[ARM] Create VMOVRRD from adjacent vector extracts	2021-04-20 15:15:43 +01:00
mve-scatter-ind8-unscaled.ll	[ARM] Create VMOVRRD from adjacent vector extracts	2021-04-20 15:15:43 +01:00
mve-scatter-ind16-scaled.ll	[ARM] Create VMOVRRD from adjacent vector extracts	2021-04-20 15:15:43 +01:00
mve-scatter-ind16-unscaled.ll	[ARM] Create VMOVRRD from adjacent vector extracts	2021-04-20 15:15:43 +01:00
mve-scatter-ind32-scaled.ll	[ARM] Create VMOVRRD from adjacent vector extracts	2021-04-20 15:15:43 +01:00
mve-scatter-ind32-unscaled.ll	[ARM] Create VMOVRRD from adjacent vector extracts	2021-04-20 15:15:43 +01:00
mve-scatter-ptrs.ll	[ARM] Create VMOVRRD from adjacent vector extracts	2021-04-20 15:15:43 +01:00
mve-selectcc.ll	[ARM] KnownBits for CSINC/CSNEG/CSINV	2021-03-04 08:40:20 +00:00
mve-sext-masked-load.ll
mve-sext.ll	[ARM] Create VMOVRRD from adjacent vector extracts	2021-04-20 15:15:43 +01:00
mve-shifts-scalar.ll	[ARM] Remove DLS lr, lr	2021-02-02 11:09:31 +00:00
mve-shifts.ll	[ARM] Create VMOVRRD from adjacent vector extracts	2021-04-20 15:15:43 +01:00
mve-shuffle.ll	[ARM] Create VMOVRRD from adjacent vector extracts	2021-04-20 15:15:43 +01:00
mve-shuffleext.ll
mve-shufflemov.ll	[ARM] Move double vector insert patterns using vins to DAG combine	2021-02-22 09:29:47 +00:00
mve-simple-arith.ll	[ARM] Create VMOVRRD from adjacent vector extracts	2021-04-20 15:15:43 +01:00
mve-soft-float-abi.ll	[ARM] Expand VMOVRRD simplification pattern	2021-04-26 12:27:38 +01:00
mve-stack.ll
mve-stacksplot.mir
mve-tailpred-loopinvariant.ll	[ARM] Recognize VIDUP from BUILDVECTORs of additions	2021-04-27 19:33:24 +01:00
mve-tp-loop.mir	[ARM] Define CPSR on MEMCPY pseudos	2021-05-14 15:06:59 +01:00
mve-vabd.ll	[ARM] Create VMOVRRD from adjacent vector extracts	2021-04-20 15:15:43 +01:00
mve-vabdus.ll	[ARM] Create VMOVRRD from adjacent vector extracts	2021-04-20 15:15:43 +01:00
mve-vaddqr.ll	[ARM] Use half directly for args/return types in test. NFC	2021-01-25 17:50:19 +00:00
mve-vaddv.ll	[ARM] Create VMOVRRD from adjacent vector extracts	2021-04-20 15:15:43 +01:00
mve-vcmp.ll	[ARM] Create VMOVRRD from adjacent vector extracts	2021-04-20 15:15:43 +01:00
mve-vcmpf.ll	[ARM] KnownBits for CSINC/CSNEG/CSINV	2021-03-04 08:40:20 +00:00
mve-vcmpfr.ll	[ARM] KnownBits for CSINC/CSNEG/CSINV	2021-03-04 08:40:20 +00:00
mve-vcmpfz.ll	[ARM] KnownBits for CSINC/CSNEG/CSINV	2021-03-04 08:40:20 +00:00
mve-vcmpr.ll	[ARM] Create VMOVRRD from adjacent vector extracts	2021-04-20 15:15:43 +01:00
mve-vcmpz.ll	[ARM] Create VMOVRRD from adjacent vector extracts	2021-04-20 15:15:43 +01:00
mve-vcreate.ll	[ARM] Simplify VMOVRRD from extracts of buildvectors	2021-02-01 16:09:25 +00:00
mve-vctp.ll
mve-vcvt16.ll
mve-vcvt.ll	[ARM] Create VMOVRRD from adjacent vector extracts	2021-04-20 15:15:43 +01:00
mve-vdup.ll	[ARM] Use half directly for args/return types in test. NFC	2021-01-25 17:50:19 +00:00
mve-vecreduce-add.ll	[ARM] Expand VMOVRRD simplification pattern	2021-04-26 12:27:38 +01:00
mve-vecreduce-addpred.ll	[ARM] Create VMOVRRD from adjacent vector extracts	2021-04-20 15:15:43 +01:00
mve-vecreduce-bit.ll	[ARM] Create VMOVRRD from adjacent vector extracts	2021-04-20 15:15:43 +01:00
mve-vecreduce-fadd.ll	[ARM] Use half directly for args/return types in test. NFC	2021-01-25 17:50:19 +00:00
mve-vecreduce-fminmax.ll	[ARM] Use half directly for args/return types in test. NFC	2021-01-25 17:50:19 +00:00
mve-vecreduce-fmul.ll	[ARM] Use half directly for args/return types in test. NFC	2021-01-25 17:50:19 +00:00
mve-vecreduce-loops.ll	[ARM] Create VMOVRRD from adjacent vector extracts	2021-04-20 15:15:43 +01:00
mve-vecreduce-mla.ll	[ARM] Expand VMOVRRD simplification pattern	2021-04-26 12:27:38 +01:00
mve-vecreduce-mlapred.ll	[ARM] Create VMOVRRD from adjacent vector extracts	2021-04-20 15:15:43 +01:00
mve-vecreduce-mul.ll	[ARM] Create VMOVRRD from adjacent vector extracts	2021-04-20 15:15:43 +01:00
mve-vector-spill.ll
mve-vfma.ll
mve-vhadd.ll	[ARM] Extra tests for MVE vhadd and vmulh. NFC	2021-05-20 14:13:39 +01:00
mve-vhaddsub.ll
mve-vidup.ll	[ARM] Recognize VIDUP from BUILDVECTORs of additions	2021-04-27 19:33:24 +01:00
mve-vld2-post.ll	[ARM] Create VMOVRRD from adjacent vector extracts	2021-04-20 15:15:43 +01:00
mve-vld2.ll	[ARM] Transfer memory operands for VLDn	2021-05-03 00:04:21 +01:00
mve-vld3.ll	[ARM] Create VMOVRRD from adjacent vector extracts	2021-04-20 15:15:43 +01:00
mve-vld4-post.ll	[ARM] Create VMOVRRD from adjacent vector extracts	2021-04-20 15:15:43 +01:00
mve-vld4.ll	[ARM] Transfer memory operands for VLDn	2021-05-03 00:04:21 +01:00
mve-vldshuffle.ll	[ARM] Extend search for increment in load/store optimizer	2021-02-15 13:17:21 +00:00
mve-vldst4.ll	[ARM] Constrain CMPZ shift combine to a single use	2021-05-13 18:31:01 +01:00
mve-vmaxnma-commute.ll	[ARM] Improve WLS lowering	2021-03-11 17:56:19 +00:00
mve-vmaxv-vminv-scalar.ll	[ARM] Create VMOVRRD from adjacent vector extracts	2021-04-20 15:15:43 +01:00
mve-vmaxv.ll
mve-vmla.ll
mve-vmovimm.ll	[ARM] Combine sub 0, csinc X, Y, CC -> csinv -X, Y, CC	2021-04-16 11:52:31 +01:00
mve-vmovn.ll	[ARM] Create VMOVRRD from adjacent vector extracts	2021-04-20 15:15:43 +01:00
mve-vmovnstore.ll	[ARM] Select VINS from vector inserts	2021-02-02 13:50:02 +00:00
mve-vmulh.ll	[ARM] Extra tests for MVE vhadd and vmulh. NFC	2021-05-20 14:13:39 +01:00
mve-vmull-loop.ll	[ARM] Create VMOVRRD from adjacent vector extracts	2021-04-20 15:15:43 +01:00
mve-vmull.ll
mve-vmulqr.ll
mve-vmvnimm.ll
mve-vpsel.ll
mve-vpt-2-blocks-1-pred.mir
mve-vpt-2-blocks-2-preds.mir
mve-vpt-2-blocks-ctrl-flow.mir
mve-vpt-2-blocks-non-consecutive-ins.mir
mve-vpt-2-blocks.mir
mve-vpt-3-blocks-kill-vpr.mir
mve-vpt-block-1-ins.mir
mve-vpt-block-2-ins.mir
mve-vpt-block-4-ins.mir
mve-vpt-block-elses.mir
mve-vpt-block-fold-vcmp.mir
mve-vpt-block-kill.mir
mve-vpt-block-optnone.mir
mve-vpt-blocks.ll
mve-vpt-from-intrinsics.ll
mve-vpt-nots.mir
mve-vpt-optimisations.mir
mve-vpt-preuse.mir
mve-vqdmulh.ll	[ARM] Create VMOVRRD from adjacent vector extracts	2021-04-20 15:15:43 +01:00
mve-vqmovn-combine.ll
mve-vqmovn.ll	[ARM] Create VMOVRRD from adjacent vector extracts	2021-04-20 15:15:43 +01:00
mve-vqshrn.ll	[ARM] Create VMOVRRD from adjacent vector extracts	2021-04-20 15:15:43 +01:00
mve-vst2-post.ll
mve-vst2.ll	[ARM] Transfer memory operands for VLDn	2021-05-03 00:04:21 +01:00
mve-vst3.ll	[ARM] Create VMOVRRD from adjacent vector extracts	2021-04-20 15:15:43 +01:00
mve-vst4-post.ll
mve-vst4.ll	[ARM] Transfer memory operands for VLDn	2021-05-03 00:04:21 +01:00
mve-vsubqr.ll
mve-widen-narrow.ll
mve-zext-masked-load.ll	[ARM] Create VMOVRRD from adjacent vector extracts	2021-04-20 15:15:43 +01:00
peephole-addsub.mir
peephole-cmp.mir
phi_prevent_copy.mir	[ARM] Prevent phi-node-elimination from generating copy above t2WhileLoopStartLR	2021-04-16 16:45:07 +01:00
pic-load.ll
postinc-distribute.mir
scavenge-lr.mir	[NFC] Move scavenge-lr.mir From AArch64 to Thumb2 test directory.	2021-01-28 10:22:31 +00:00
schedm7-hazard.ll
segmented-stacks.ll
setjmp_longjmp.ll
shift_parts.ll
srem-seteq-illegal-types.ll	Support {S,U}REMEqFold before legalization	2021-04-01 01:35:41 +03:00
stack_guard_remat.ll
store-prepostinc.mir	[ARM] Expand the range of allowed post-incs in load/store optimizer	2021-02-24 08:46:15 +00:00
t2-teq-reduce.mir
t2peephole-t2ADDrr-to-t2ADDri.ll
t2sizereduction.mir
tail-call-r9.ll
tbb-removeadd.mir
thumb2-adc.ll
thumb2-add2.ll
thumb2-add3.ll
thumb2-add4.ll
thumb2-add5.ll
thumb2-add6.ll
thumb2-add.ll
thumb2-and2.ll
thumb2-and.ll
thumb2-asr2.ll
thumb2-asr.ll
thumb2-bcc.ll
thumb2-bfc.ll
thumb2-bic.ll
thumb2-branch.ll
thumb2-call-tc.ll
thumb2-call.ll
thumb2-cbnz.ll
thumb2-clz.ll
thumb2-cmn2.ll
thumb2-cmn.ll
thumb2-cmp.ll
thumb2-cpsr-liveness.ll
thumb2-eor2.ll
thumb2-eor.ll
thumb2-execute-only-prologue.ll
thumb2-ifcvt1-tc.ll
thumb2-ifcvt1.ll
thumb2-ifcvt2.ll
thumb2-ifcvt3.ll
thumb2-jtb.ll
thumb2-ldm.ll
thumb2-ldr_ext.ll
thumb2-ldr_post.ll
thumb2-ldr_pre.ll
thumb2-ldr.ll
thumb2-ldrb.ll
thumb2-ldrd.ll
thumb2-ldrh.ll
thumb2-lsl2.ll
thumb2-lsl.ll
thumb2-lsr2.ll
thumb2-lsr3.ll
thumb2-lsr.ll
thumb2-mla.ll
thumb2-mls.ll
thumb2-mov.ll
thumb2-mul.ll
thumb2-mulhi.ll
thumb2-mvn2.ll
thumb2-mvn.ll
thumb2-neg.ll
thumb2-orn2.ll
thumb2-orn.ll
thumb2-orr2.ll
thumb2-orr.ll
thumb2-pack.ll
thumb2-rev16.ll
thumb2-rev.ll
thumb2-ror.ll
thumb2-rsb2.ll
thumb2-rsb.ll
thumb2-sbc.ll
thumb2-select_xform.ll
thumb2-select.ll
thumb2-shifter.ll
thumb2-smla.ll
thumb2-smul.ll
thumb2-spill-q.ll
thumb2-str_post.ll
thumb2-str_pre.ll
thumb2-str.ll
thumb2-strb.ll
thumb2-strh.ll
thumb2-sub2.ll
thumb2-sub3.ll
thumb2-sub4.ll
thumb2-sub5.ll
thumb2-sub.ll
thumb2-sxt_rot.ll
thumb2-sxt-uxt.ll
thumb2-tbb.ll
thumb2-tbh.ll
thumb2-teq2.ll
thumb2-teq.ll
thumb2-tst2.ll
thumb2-tst.ll
thumb2-uxt_rot.ll
thumb2-uxtb.ll
tls1.ll
tls2.ll
tpsoft.ll
umulo-64-legalisation-lowering.ll
umulo-128-legalisation-lowering.ll
unreachable-large-offset-gep.ll
urem-seteq-illegal-types.ll	Support {S,U}REMEqFold before legalization	2021-04-01 01:35:41 +03:00
v8_deprecate_IT.ll
v8_IT_1.ll
v8_IT_2.ll
v8_IT_3.ll
v8_IT_4.ll
v8_IT_5.ll
v8_IT_6.ll
vmovdrroffset.ll
vqabs.ll
vqneg.ll