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mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-25 04:02:41 +01:00
llvm-mirror/lib/Target/Sparc
Misha Brukman 8c9be85d5d Fixed the number translation scheme for the integer condition code registers: it
now works in instructions which require a 2-bit or 3-bit INTcc code.

Incidentally, that means that the representation of INTcc registers is now the
same in both integer and FP instructions. Thus, code became much simpler and
cleaner.

llvm-svn: 7185
2003-07-16 20:30:40 +00:00
..
.cvsignore Since there is now another derived .inc file, ignore them all. 2003-05-29 20:15:27 +00:00
EmitAssembly.cpp The word separate' only has one e'. 2003-07-14 17:20:40 +00:00
EmitBytecodeToAssembly.cpp
Makefile Merged in autoconf branch. This provides configuration via the autoconf 2003-06-30 21:59:07 +00:00
MappingInfo.cpp lib/CodeGen/Mapping/MappingInfo.cpp: 2003-06-04 22:07:12 +00:00
MappingInfo.h Add file comment. Include <vector> and <string>. Update include guards 2003-06-04 22:02:47 +00:00
PeepholeOpts.cpp Cleaned up code layout; no functional changes. 2003-05-23 19:20:57 +00:00
PreSelection.cpp (1) Major bug fix: DecomposeArrayRef() replaces its argument instr. and 2003-07-02 01:23:15 +00:00
PrologEpilogCodeInserter.cpp * Changed Bcc instructions to behave like BPcc instructions 2003-06-06 09:52:23 +00:00
Sparc.burg.in Fold cast-to-bool into not. Later, this should also be folded into other 2003-07-10 19:47:42 +00:00
Sparc.cpp lib/Target/Sparc/Sparc.cpp: 2003-06-18 21:14:23 +00:00
SparcInstr.def RDCCR defines arg. #1, not arg. #2. 2003-06-20 11:32:11 +00:00
SparcInstrInfo.cpp Bug fix in creating constants: need 1U << 31, not 1 << 31. 2003-07-10 19:48:19 +00:00
SparcInstrSelection.cpp Several important bug fixes: 2003-07-10 20:07:54 +00:00
SparcInstrSelectionSupport.h * Changed Bcc instructions to behave like BPcc instructions 2003-06-06 09:52:23 +00:00
SparcInternals.h Moved RegClassIDs enum to be next to the RegTypes enum. 2003-07-07 16:52:39 +00:00
SparcRegClassInfo.cpp Several fixes to handling of int CC register: 2003-07-10 19:42:11 +00:00
SparcRegClassInfo.h Major bug fix though it happened rarely (only on a compare after an 2003-07-06 20:13:59 +00:00
SparcRegInfo.cpp Several fixes to handling of int CC register: 2003-07-10 19:42:11 +00:00
SparcV9_F2.td Encode predict = 1 by default, because the Sparc assembler does this. 2003-07-15 21:26:49 +00:00
SparcV9_F3.td No need for a second immediate field if the class already inherits one. 2003-07-15 21:27:14 +00:00
SparcV9_F4.td The name should really be `simm11' to follow the naming convention, but this has 2003-07-16 20:27:44 +00:00
SparcV9_Reg.td * Broke up SparcV9.td into separate files as it was getting unmanageable 2003-05-29 03:31:43 +00:00
SparcV9.td Elaborated assembly syntax of instructions in the comments. 2003-07-07 22:18:42 +00:00
SparcV9CodeEmitter.cpp Fixed the number translation scheme for the integer condition code registers: it 2003-07-16 20:30:40 +00:00
SparcV9CodeEmitter.h Fixed the number translation scheme for the integer condition code registers: it 2003-07-16 20:30:40 +00:00
StackSlots.cpp Rename MachineInstrInfo -> TargetInstrInfo 2003-01-14 22:00:31 +00:00
UltraSparcSchedInfo.cpp Added 'r' and 'i' versions to WRCCR. 2003-06-06 09:52:58 +00:00