Prakhar Bahuguna 7f12177e67 Correct the upper bound for a CBZ/CBNZ branch target. ...

Summary:
Fix for the upper bound check that was causing a build failure.

Reviewers: olista01, rengolin, t.p.northover

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D23501

llvm-svn: 278789

2016-08-16 10:41:56 +00:00

..

AArch64

AArch64: TableGenerate system instruction operands.

2016-07-05 21:23:04 +00:00

AMDGPU

[AMDGPU] refactor DS instruction definitions. NFC.

2016-08-01 14:21:30 +00:00

ARM

Correct the upper bound for a CBZ/CBNZ branch target.

2016-08-16 10:41:56 +00:00

AsmParser

Revert r276895 "[MC][X86] Fix Intel Operand assembly parsing for .set ids"

2016-08-01 23:00:01 +00:00

COFF

[codeview] Shrink inlined call site line info tables

2016-07-14 23:47:15 +00:00

Disassembler

[AMDGPU] fix failure on printing of non-existing instruction operands.

2016-08-15 10:56:48 +00:00

ELF

Add initial support for R_386_GOT32X.

2016-07-06 21:19:11 +00:00

Hexagon

Remove redundant -mattr options from llvm-objdump commands.

2016-06-16 15:47:19 +00:00

Lanai

[lanai] Add more tests for assembly of conditional ALU ops

2016-07-11 17:58:16 +00:00

MachO

CodeGen: Use PLT relocations for relative references to unnamed_addr functions.

2016-04-22 20:40:10 +00:00

Markup

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Mips

Re-commit r277988: [mips][ias] Fix all the hacks related to MIPS-specific unary operators (%hi/%lo/%gp_rel/etc.).

2016-08-08 11:50:25 +00:00

PowerPC

Add aliases for mfvrsave/mtvrsave.

2016-06-09 23:27:48 +00:00

Sparc

Don't pass a Reloc::Model to MC.

2016-05-18 11:58:50 +00:00

SystemZ

[SystemZ] Add support for the .insn directive

2016-08-08 15:13:08 +00:00

X86

[X86] Improve code size on X86 segment moves

2016-08-08 18:01:04 +00:00