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llvm-mirror/test/CodeGen
Richard Sandiford 8d6edc5218 [SystemZ] Tweak integer comparison code
The architecture has many comparison instructions, including some that
extend one of the operands.  The signed comparison instructions use sign
extensions and the unsigned comparison instructions use zero extensions.
In cases where we had a free choice between signed or unsigned comparisons,
we were trying to decide at lowering time which would best fit the available
instructions, taking things like extension type into account.  The code
to do that was getting increasingly hairy and was also making some bad
decisions.  E.g. when comparing the result of two LLCs, it is better to use
CR rather than CLR, since CR can be fused with a branch while CLR can't.

This patch removes the lowering code and instead adds an operand to
integer comparisons to say whether signed comparison is required,
whether unsigned comparison is required, or whether either is OK.
We can then leave the choice of instruction up to the normal isel code.

llvm-svn: 190138
2013-09-06 11:51:39 +00:00
..
AArch64 Inplement aarch64 neon instructions in AdvSIMD(shift). About 24 shift instructions: 2013-09-04 09:28:24 +00:00
ARM [ARMv8] Implement the new DMB/DSB operands. 2013-09-05 15:35:24 +00:00
CPP
Generic
Hexagon Debug Info: add an identifier field to DICompositeType. 2013-08-26 22:39:55 +00:00
Inputs Debug Info: add an identifier field to DICompositeType. 2013-08-26 22:39:55 +00:00
Mips Make sure we don't generate stubs for any of these functions because they 2013-09-01 04:12:59 +00:00
MSP430
NVPTX [NVPTX] Re-enable assembly printing support for inline assembly 2013-08-24 01:17:23 +00:00
PowerPC [PowerPC] Call support for fast-isel. 2013-08-30 22:18:55 +00:00
R600 Teach CodeGenPrepare about address spaces 2013-09-06 00:18:43 +00:00
SPARC [Sparc] Correctly handle call to functions with ReturnsTwice attribute. 2013-09-05 05:32:16 +00:00
SystemZ [SystemZ] Tweak integer comparison code 2013-09-06 11:51:39 +00:00
Thumb ARM: Use "dmb sy" for barriers on M-class CPUs 2013-08-28 14:39:19 +00:00
Thumb2 ARM: make sure ARM-mode pseudo-inst requires IsARM 2013-08-23 10:16:39 +00:00
X86 [X86] Perform VSELECT DAG combines also before DAG type legalization. 2013-09-05 23:02:56 +00:00
XCore