..
AsmParser
[AArch64AsmParser] Fix type-limits warning for VectorIndex.
2021-02-08 15:35:30 +00:00
Disassembler
[AArch64] Adding the v8.7-A LD64B/ST64B Accelerator extension
2020-12-17 13:46:23 +00:00
GISel
GlobalISel: Add default implementation of assignValueToReg
2021-03-03 09:29:53 -05:00
MCTargetDesc
[AArch64][SVE] Asm: Fix supported immediates for DUP/CPY
2021-02-11 08:14:15 +00:00
TargetInfo
llvmbuildectomy - replace llvm-build by plain cmake
2020-11-13 10:35:24 +01:00
Utils
[ARM][AArch64] Adding basic support for the v8.7-A architecture
2020-12-17 13:45:08 +00:00
AArch64.h
[AArch64] Homogeneous Prolog and Epilog Size Optimization
2021-02-02 14:57:26 -08:00
AArch64.td
[AArch64] Add some missing Neoverse features
2021-02-19 09:18:35 +00:00
AArch64A53Fix835769.cpp
AArch64A57FPLoadBalancing.cpp
AArch64AdvSIMDScalarPass.cpp
[AArch64] Update a code comment incorrectly referring to zero_reg. NFC
2020-08-20 14:36:59 +02:00
AArch64AsmPrinter.cpp
[MC][ELF] Support for zero flag section groups
2021-02-16 14:23:40 -08:00
AArch64BranchTargets.cpp
[AArch64] PAC/BTI code generation for LLVM generated functions
2020-09-25 11:47:14 +01:00
AArch64CallingConvention.cpp
[SVE] Deal with SVE tuple call arguments correctly when running out of registers
2020-11-12 08:41:50 +00:00
AArch64CallingConvention.h
AArch64CallingConvention.td
AArch64CleanupLocalDynamicTLSPass.cpp
AArch64CollectLOH.cpp
[AArch64] Fix emitting an AdrpAddLdr LOH when there's a potential clobber of the
2021-03-01 13:52:57 -08:00
AArch64Combine.td
Recommit "[AArch64][GlobalISel] Match G_SHUFFLE_VECTOR -> insert elt + extract elt"
2021-02-23 11:55:16 -08:00
AArch64CompressJumpTables.cpp
[AArch64] Don't try to compress jump tables if there are any inline asm instructions.
2020-12-10 12:20:02 -08:00
AArch64CondBrTuning.cpp
AArch64ConditionalCompares.cpp
AArch64ConditionOptimizer.cpp
AArch64DeadRegisterDefinitionsPass.cpp
AArch64ExpandImm.cpp
AArch64ExpandImm.h
AArch64ExpandPseudoInsts.cpp
[AArch64][SVE] Add patterns to generate FMLA/FMLS/FNMLA/FNMLS/FMAD
2021-02-18 16:55:16 +00:00
AArch64FalkorHWPFFix.cpp
Small fixes for "[LoopInfo] empty() -> isInnermost(), add isOutermost()"
2020-09-22 23:59:34 +03:00
AArch64FastISel.cpp
AArch64: relax address-space assertion in FastISel.
2021-02-25 10:15:55 +00:00
AArch64FrameLowering.cpp
[AArch64] Do not fold SP adjustments into pre-increment addr modes if it overflows the redzone.
2021-02-24 09:55:48 -08:00
AArch64FrameLowering.h
[AArch64] Homogeneous Prolog and Epilog Size Optimization
2021-02-02 14:57:26 -08:00
AArch64GenRegisterBankInfo.def
AArch64InstrAtomics.td
AArch64InstrFormats.td
[CodeGen] Fix issues with subvector intrinsic index types
2021-03-01 10:28:21 +00:00
AArch64InstrGISel.td
[AArch64][GlobalISel] Add selection support for fpr bank source variants of G_SITOFP and G_UITOFP.
2021-01-14 19:31:19 -08:00
AArch64InstrInfo.cpp
[GlobalISel] Propagate extends through G_PHIs into the incoming value blocks.
2021-02-12 11:52:52 -08:00
AArch64InstrInfo.h
[GlobalISel] Propagate extends through G_PHIs into the incoming value blocks.
2021-02-12 11:52:52 -08:00
AArch64InstrInfo.td
[CodeGen] Fix issues with subvector intrinsic index types
2021-03-01 10:28:21 +00:00
AArch64ISelDAGToDAG.cpp
[AArch64] Adding ACLE intrinsics for the LS64 extension
2021-01-14 09:43:58 +00:00
AArch64ISelLowering.cpp
[AArch64] Add combine for add(udot(0, x, y), z) -> udot(z, x, y).
2021-03-01 12:53:34 +00:00
AArch64ISelLowering.h
[AArch64] Do not fold SP adjustments into pre-increment addr modes if it overflows the redzone.
2021-02-24 09:55:48 -08:00
AArch64LoadStoreOptimizer.cpp
[AArch64] Do not fold SP adjustments into pre-increment addr modes if it overflows the redzone.
2021-02-24 09:55:48 -08:00
AArch64LowerHomogeneousPrologEpilog.cpp
AArch64LowerHomogeneousPrologEpilog.cpp - fix Wdocumentation warning. NFCI.
2021-02-05 11:34:43 +00:00
AArch64MachineFunctionInfo.cpp
[AArch64] PAC/BTI code generation for LLVM generated functions
2020-09-25 11:47:14 +01:00
AArch64MachineFunctionInfo.h
[AArch64][SVE] Allow accesses to SVE stack objects to use frame pointer
2021-01-28 12:39:57 +00:00
AArch64MacroFusion.cpp
[AArch64] Add Cortex CPU subtarget features for instruction fusion.
2021-01-25 09:11:29 +00:00
AArch64MacroFusion.h
[llvm] Add missing header guards (NFC)
2021-01-30 09:53:42 -08:00
AArch64MCInstLower.cpp
[AArch64] [Windows] Properly add :lo12: reloc specifiers when generating assembly
2021-01-12 23:56:03 +02:00
AArch64MCInstLower.h
AArch64PBQPRegAlloc.cpp
AArch64PBQPRegAlloc.h
AArch64PerfectShuffle.h
AArch64PfmCounters.td
AArch64PromoteConstant.cpp
AArch64RedundantCopyElimination.cpp
[AArch64] Fix Copy Elemination for negative values
2020-12-18 13:30:46 +00:00
AArch64RegisterBanks.td
AArch64RegisterInfo.cpp
Change materializeFrameBaseRegister() to return register
2021-01-22 15:51:06 -08:00
AArch64RegisterInfo.h
Change materializeFrameBaseRegister() to return register
2021-01-22 15:51:06 -08:00
AArch64RegisterInfo.td
[AArch64] Add a GPR64x8 register class
2020-12-17 13:45:46 +00:00
AArch64SchedA53.td
AArch64SchedA55.td
[AArch64] Enable Cortex-A55 schedmodel
2020-11-30 19:28:34 +00:00
AArch64SchedA57.td
[AARCH64] Improve accumulator forwarding for Cortex-A57 model
2021-01-04 10:58:43 +00:00
AArch64SchedA57WriteRes.td
[AARCH64] Improve accumulator forwarding for Cortex-A57 model
2021-01-04 10:58:43 +00:00
AArch64SchedA64FX.td
[AArch64] Add Fujitsu A64FX scheduling model
2021-01-15 17:14:04 +09:00
AArch64SchedCyclone.td
AArch64SchedExynosM3.td
AArch64SchedExynosM4.td
AArch64SchedExynosM5.td
AArch64SchedFalkor.td
AArch64SchedFalkorDetails.td
AArch64SchedKryo.td
AArch64SchedKryoDetails.td
AArch64SchedPredExynos.td
AArch64SchedPredicates.td
AArch64SchedThunderX2T99.td
AArch64SchedThunderX3T110.td
AArch64SchedThunderX.td
AArch64SchedTSV110.td
[AArch64] Add pipeline model for HiSilicon's TSV110
2020-11-07 01:23:00 +03:00
AArch64Schedule.td
AArch64SelectionDAGInfo.cpp
[AArch64][SVE] Add patterns to generate FMLA/FMLS/FNMLA/FNMLS/FMAD
2021-02-18 16:55:16 +00:00
AArch64SelectionDAGInfo.h
[AArch64][SVE] Add patterns to generate FMLA/FMLS/FNMLA/FNMLS/FMAD
2021-02-18 16:55:16 +00:00
AArch64SIMDInstrOpt.cpp
[AArch64] reuse another map iterator. NFC
2020-09-28 11:30:21 -07:00
AArch64SLSHardening.cpp
AArch64SpeculationHardening.cpp
AArch64StackTagging.cpp
[llvm] Use llvm::lower_bound and llvm::upper_bound (NFC)
2021-01-05 21:15:59 -08:00
AArch64StackTaggingPreRA.cpp
[MTE] Pin the tagged base pointer to one of the stack slots.
2020-10-15 12:50:16 -07:00
AArch64StorePairSuppress.cpp
AArch64Subtarget.cpp
AArch64: add apple-a14 as a CPU
2021-01-19 14:04:53 +00:00
AArch64Subtarget.h
[AArch64] Add Cortex CPU subtarget features for instruction fusion.
2021-01-25 09:11:29 +00:00
AArch64SVEInstrInfo.td
[AArch64][SVE] Add patterns to generate FMLA/FMLS/FNMLA/FNMLS/FMAD
2021-02-18 16:55:16 +00:00
AArch64SystemOperands.td
[AArch64] Add +pauth archictecture option, allowing the v8.3a pointer authentication extension.
2021-01-08 13:21:11 +00:00
AArch64TargetMachine.cpp
[AArch64][GlobalISel] Enable use of the optsize predicate in the selector.
2021-03-02 12:55:51 -08:00
AArch64TargetMachine.h
Support addrspacecast initializers with isNoopAddrSpaceCast
2020-07-31 10:42:43 -04:00
AArch64TargetObjectFile.cpp
AArch64TargetObjectFile.h
AArch64TargetTransformInfo.cpp
[AArch64] Add abs intrinsic costs
2021-02-25 09:31:52 +00:00
AArch64TargetTransformInfo.h
[SVE] Add support for scalable vectorization of loops with int/fast FP reductions
2021-02-16 13:50:06 +00:00
CMakeLists.txt
[AArch64] Homogeneous Prolog and Epilog Size Optimization
2021-02-02 14:57:26 -08:00
SVEInstrFormats.td
[AArch64][SVE] Add patterns to generate FMLA/FMLS/FNMLA/FNMLS/FMAD
2021-02-18 16:55:16 +00:00
SVEIntrinsicOpts.cpp
[AArch64][SVE] Coalesce ptrue instrinsic calls where possible
2021-02-05 10:43:28 +00:00
