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llvm-mirror/lib/Target/AArch64
Sander de Smalen 3a95e5caa2 [AArch64][SVE] NFCI: Choose consistent naming for predicated SDAG nodes
This patch proposes a naming convention for operations that take
a general predicate (and are thus predicated) that specifies
what happens to the false lanes.

Currently the _PRED suffix is used, which doesn't really say much other
than that it takes a predicate. In some instances this means it has
merging predication and in other cases it means zeroing-predication.

This patch also changes the order of operands to
AArch64ISD::DUP_MERGE_PASSTHRU, to pass the predicate as the first
operand, which is in line with all other predicates nodes. It takes the
passthru value as an explicit passthru value, which is always passed as
the last operand.

Reviewers: paulwalker-arm, cameron.mcinally, eli.friedman, dancgr, efriedma

Reviewed By: paulwalker-arm

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D81850
2020-06-29 13:37:30 +01:00
..
AsmParser
Disassembler [AArch64] Emit warning when disassembling unpredictable LDRAA and LDRAB 2020-06-25 15:56:36 +01:00
GISel [AArch64][GlobalISel] Fix extended shift addressing mode selection not handling sxth. 2020-06-25 17:24:32 -07:00
MCTargetDesc
TargetInfo
Utils
AArch64.h
AArch64.td
AArch64A53Fix835769.cpp
AArch64A57FPLoadBalancing.cpp
AArch64AdvSIMDScalarPass.cpp
AArch64AsmPrinter.cpp
AArch64BranchTargets.cpp
AArch64CallingConvention.cpp
AArch64CallingConvention.h
AArch64CallingConvention.td
AArch64CleanupLocalDynamicTLSPass.cpp
AArch64CollectLOH.cpp
AArch64Combine.td
AArch64CompressJumpTables.cpp
AArch64CondBrTuning.cpp
AArch64ConditionalCompares.cpp
AArch64ConditionOptimizer.cpp
AArch64DeadRegisterDefinitionsPass.cpp
AArch64ExpandImm.cpp
AArch64ExpandImm.h
AArch64ExpandPseudoInsts.cpp
AArch64FalkorHWPFFix.cpp
AArch64FastISel.cpp
AArch64FrameLowering.cpp
AArch64FrameLowering.h
AArch64GenRegisterBankInfo.def
AArch64InstrAtomics.td
AArch64InstrFormats.td [AArch64] Emit warning when disassembling unpredictable LDRAA and LDRAB 2020-06-25 15:56:36 +01:00
AArch64InstrGISel.td
AArch64InstrInfo.cpp
AArch64InstrInfo.h
AArch64InstrInfo.td
AArch64ISelDAGToDAG.cpp [AArch64][SVE] NFCI: Choose consistent naming for predicated SDAG nodes 2020-06-29 13:37:30 +01:00
AArch64ISelLowering.cpp [AArch64][SVE] NFCI: Choose consistent naming for predicated SDAG nodes 2020-06-29 13:37:30 +01:00
AArch64ISelLowering.h [AArch64][SVE] NFCI: Choose consistent naming for predicated SDAG nodes 2020-06-29 13:37:30 +01:00
AArch64LoadStoreOptimizer.cpp
AArch64MachineFunctionInfo.cpp
AArch64MachineFunctionInfo.h
AArch64MacroFusion.cpp
AArch64MacroFusion.h
AArch64MCInstLower.cpp
AArch64MCInstLower.h
AArch64PBQPRegAlloc.cpp
AArch64PBQPRegAlloc.h
AArch64PerfectShuffle.h
AArch64PfmCounters.td
AArch64PromoteConstant.cpp
AArch64RedundantCopyElimination.cpp
AArch64RegisterBanks.td
AArch64RegisterInfo.cpp
AArch64RegisterInfo.h
AArch64RegisterInfo.td
AArch64SchedA53.td
AArch64SchedA57.td
AArch64SchedA57WriteRes.td
AArch64SchedCyclone.td
AArch64SchedExynosM3.td
AArch64SchedExynosM4.td
AArch64SchedExynosM5.td
AArch64SchedFalkor.td
AArch64SchedFalkorDetails.td
AArch64SchedKryo.td
AArch64SchedKryoDetails.td
AArch64SchedPredExynos.td
AArch64SchedPredicates.td
AArch64SchedThunderX2T99.td
AArch64SchedThunderX3T110.td
AArch64SchedThunderX.td
AArch64Schedule.td
AArch64SelectionDAGInfo.cpp
AArch64SelectionDAGInfo.h
AArch64SIMDInstrOpt.cpp
AArch64SLSHardening.cpp
AArch64SpeculationHardening.cpp
AArch64StackOffset.h
AArch64StackTagging.cpp
AArch64StackTaggingPreRA.cpp
AArch64StorePairSuppress.cpp
AArch64Subtarget.cpp
AArch64Subtarget.h
AArch64SVEInstrInfo.td [AArch64][SVE] NFCI: Choose consistent naming for predicated SDAG nodes 2020-06-29 13:37:30 +01:00
AArch64SystemOperands.td
AArch64TargetMachine.cpp
AArch64TargetMachine.h
AArch64TargetObjectFile.cpp
AArch64TargetObjectFile.h
AArch64TargetTransformInfo.cpp [SVE] Code generation for fixed length vector adds. 2020-06-26 19:54:41 +00:00
AArch64TargetTransformInfo.h [Alignment][NFC] Migrate TTI::getInterleavedMemoryOpCost to Align 2020-06-26 11:00:53 +00:00
CMakeLists.txt
LLVMBuild.txt
SVEInstrFormats.td [AArch64][SVE] NFCI: Choose consistent naming for predicated SDAG nodes 2020-06-29 13:37:30 +01:00
SVEIntrinsicOpts.cpp