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https://github.com/RPCS3/llvm-mirror.git
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0212e0df47
instructions to help disassembly. We also changed the output of the addressing modes to omit the '+' from the assembler syntax #+/-<imm> or +/-<Rm>. See, for example, A8.6.57/58/60. And modified test cases to not expect '+' in +reg or #+num. For example, ; CHECK: ldr.w r9, [r7, #28] llvm-svn: 98745
72 lines
1.5 KiB
LLVM
72 lines
1.5 KiB
LLVM
; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
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define i16 @f1(i16* %v) {
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entry:
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; CHECK: f1:
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; CHECK: ldrh r0, [r0]
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%tmp = load i16* %v
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ret i16 %tmp
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}
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define i16 @f2(i16* %v) {
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entry:
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; CHECK: f2:
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; CHECK: ldrh.w r0, [r0, #2046]
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%tmp2 = getelementptr i16* %v, i16 1023
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%tmp = load i16* %tmp2
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ret i16 %tmp
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}
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define i16 @f3(i16* %v) {
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entry:
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; CHECK: f3:
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; CHECK: mov.w r1, #4096
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; CHECK: ldrh r0, [r0, r1]
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%tmp2 = getelementptr i16* %v, i16 2048
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%tmp = load i16* %tmp2
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ret i16 %tmp
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}
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define i16 @f4(i32 %base) {
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entry:
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; CHECK: f4:
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; CHECK: ldrh r0, [r0, #-128]
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%tmp1 = sub i32 %base, 128
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%tmp2 = inttoptr i32 %tmp1 to i16*
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%tmp3 = load i16* %tmp2
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ret i16 %tmp3
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}
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define i16 @f5(i32 %base, i32 %offset) {
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entry:
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; CHECK: f5:
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; CHECK: ldrh r0, [r0, r1]
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%tmp1 = add i32 %base, %offset
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%tmp2 = inttoptr i32 %tmp1 to i16*
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%tmp3 = load i16* %tmp2
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ret i16 %tmp3
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}
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define i16 @f6(i32 %base, i32 %offset) {
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entry:
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; CHECK: f6:
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; CHECK: ldrh.w r0, [r0, r1, lsl #2]
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%tmp1 = shl i32 %offset, 2
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%tmp2 = add i32 %base, %tmp1
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%tmp3 = inttoptr i32 %tmp2 to i16*
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%tmp4 = load i16* %tmp3
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ret i16 %tmp4
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}
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define i16 @f7(i32 %base, i32 %offset) {
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entry:
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; CHECK: f7:
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; CHECK: lsrs r1, r1, #2
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; CHECK: ldrh r0, [r0, r1]
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%tmp1 = lshr i32 %offset, 2
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%tmp2 = add i32 %base, %tmp1
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%tmp3 = inttoptr i32 %tmp2 to i16*
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%tmp4 = load i16* %tmp3
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ret i16 %tmp4
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}
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