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95037fa9f6
Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
261 lines
6.2 KiB
LLVM
261 lines
6.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV32I
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV64I
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; Materializing constants
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; TODO: It would be preferable if anyext constant returns were sign rather
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; than zero extended. See PR39092. For now, mark returns as explicitly signext
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; (this matches what Clang would generate for equivalent C/C++ anyway).
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define signext i32 @zero() nounwind {
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; RV32I-LABEL: zero:
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; RV32I: # %bb.0:
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; RV32I-NEXT: mv a0, zero
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: zero:
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; RV64I: # %bb.0:
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; RV64I-NEXT: mv a0, zero
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; RV64I-NEXT: ret
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ret i32 0
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}
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define signext i32 @pos_small() nounwind {
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; RV32I-LABEL: pos_small:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi a0, zero, 2047
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: pos_small:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi a0, zero, 2047
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; RV64I-NEXT: ret
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ret i32 2047
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}
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define signext i32 @neg_small() nounwind {
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; RV32I-LABEL: neg_small:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi a0, zero, -2048
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: neg_small:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi a0, zero, -2048
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; RV64I-NEXT: ret
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ret i32 -2048
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}
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define signext i32 @pos_i32() nounwind {
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; RV32I-LABEL: pos_i32:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a0, 423811
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; RV32I-NEXT: addi a0, a0, -1297
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: pos_i32:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lui a0, 423811
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; RV64I-NEXT: addiw a0, a0, -1297
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; RV64I-NEXT: ret
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ret i32 1735928559
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}
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define signext i32 @neg_i32() nounwind {
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; RV32I-LABEL: neg_i32:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a0, 912092
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; RV32I-NEXT: addi a0, a0, -273
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: neg_i32:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lui a0, 912092
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; RV64I-NEXT: addiw a0, a0, -273
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; RV64I-NEXT: ret
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ret i32 -559038737
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}
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define signext i32 @pos_i32_hi20_only() nounwind {
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; RV32I-LABEL: pos_i32_hi20_only:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a0, 16
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: pos_i32_hi20_only:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lui a0, 16
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; RV64I-NEXT: ret
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ret i32 65536
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}
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define signext i32 @neg_i32_hi20_only() nounwind {
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; RV32I-LABEL: neg_i32_hi20_only:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a0, 1048560
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: neg_i32_hi20_only:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lui a0, 1048560
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; RV64I-NEXT: ret
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ret i32 -65536
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}
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define i64 @imm64_1() nounwind {
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; RV32I-LABEL: imm64_1:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a0, 524288
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; RV32I-NEXT: mv a1, zero
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: imm64_1:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi a0, zero, 1
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; RV64I-NEXT: slli a0, a0, 31
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; RV64I-NEXT: ret
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ret i64 2147483648
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}
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; TODO: This and similar constants with all 0s in the upper bits and all 1s in
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; the lower bits could be lowered to addi a0, zero, -1 followed by a logical
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; right shift.
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define i64 @imm64_2() nounwind {
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; RV32I-LABEL: imm64_2:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi a0, zero, -1
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; RV32I-NEXT: mv a1, zero
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: imm64_2:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi a0, zero, 1
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; RV64I-NEXT: slli a0, a0, 32
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; RV64I-NEXT: addi a0, a0, -1
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; RV64I-NEXT: ret
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ret i64 4294967295
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}
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define i64 @imm64_3() nounwind {
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; RV32I-LABEL: imm64_3:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi a1, zero, 1
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; RV32I-NEXT: mv a0, zero
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: imm64_3:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi a0, zero, 1
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; RV64I-NEXT: slli a0, a0, 32
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; RV64I-NEXT: ret
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ret i64 4294967296
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}
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define i64 @imm64_4() nounwind {
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; RV32I-LABEL: imm64_4:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a1, 524288
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; RV32I-NEXT: mv a0, zero
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: imm64_4:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi a0, zero, -1
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; RV64I-NEXT: slli a0, a0, 63
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; RV64I-NEXT: ret
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ret i64 9223372036854775808
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}
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define i64 @imm64_5() nounwind {
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; RV32I-LABEL: imm64_5:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a1, 524288
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; RV32I-NEXT: mv a0, zero
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: imm64_5:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi a0, zero, -1
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; RV64I-NEXT: slli a0, a0, 63
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; RV64I-NEXT: ret
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ret i64 -9223372036854775808
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}
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define i64 @imm64_6() nounwind {
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; RV32I-LABEL: imm64_6:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a0, 74565
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; RV32I-NEXT: addi a1, a0, 1656
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; RV32I-NEXT: mv a0, zero
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: imm64_6:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lui a0, 9321
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; RV64I-NEXT: addiw a0, a0, -1329
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; RV64I-NEXT: slli a0, a0, 35
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; RV64I-NEXT: ret
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ret i64 1311768464867721216
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}
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define i64 @imm64_7() nounwind {
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; RV32I-LABEL: imm64_7:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a0, 45056
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; RV32I-NEXT: addi a0, a0, 15
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; RV32I-NEXT: lui a1, 458752
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: imm64_7:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi a0, zero, 7
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; RV64I-NEXT: slli a0, a0, 36
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; RV64I-NEXT: addi a0, a0, 11
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; RV64I-NEXT: slli a0, a0, 24
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; RV64I-NEXT: addi a0, a0, 15
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; RV64I-NEXT: ret
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ret i64 8070450532432478223
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}
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; TODO: it can be preferable to put constants that are expensive to materialise
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; into the constant pool, especially for -Os.
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define i64 @imm64_8() nounwind {
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; RV32I-LABEL: imm64_8:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a0, 633806
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; RV32I-NEXT: addi a0, a0, -272
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; RV32I-NEXT: lui a1, 74565
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; RV32I-NEXT: addi a1, a1, 1656
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: imm64_8:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lui a0, 583
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; RV64I-NEXT: addiw a0, a0, -1875
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; RV64I-NEXT: slli a0, a0, 14
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; RV64I-NEXT: addi a0, a0, -947
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; RV64I-NEXT: slli a0, a0, 12
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; RV64I-NEXT: addi a0, a0, 1511
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; RV64I-NEXT: slli a0, a0, 13
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; RV64I-NEXT: addi a0, a0, -272
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; RV64I-NEXT: ret
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ret i64 1311768467463790320
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}
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define i64 @imm64_9() nounwind {
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; RV32I-LABEL: imm64_9:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi a0, zero, -1
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; RV32I-NEXT: addi a1, zero, -1
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: imm64_9:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi a0, zero, -1
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; RV64I-NEXT: ret
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ret i64 -1
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}
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