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a3d65c2594
Summary: NFC. Adding MC regressions tests to cover all the SSE ISA sets as follows: SSE, SSE2, SSE3, SSE4, SSE42, SSEMXCSR, SSE_PREFETCH, SSSE3 This patch is part of a larger task to cover MC encoding of all X86 ISA Sets. See revision: https://reviews.llvm.org/D39952 Patch by Gadi Haber and Wang Tianqing Reviewers: RKSimon, zvi, craig.topper, AndreiGrischenko, gadi.haber, LuoYuanke Reviewed By: craig.topper Subscribers: jfb, llvm-commits Differential Revision: https://reviews.llvm.org/D40387 llvm-svn: 352955
51 lines
1.4 KiB
ArmAsm
51 lines
1.4 KiB
ArmAsm
// RUN: llvm-mc -triple i386-unknown-unknown --show-encoding %s | FileCheck %s
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// CHECK: ldmxcsr -485498096(%edx,%eax,4)
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// CHECK: encoding: [0x0f,0xae,0x94,0x82,0x10,0xe3,0x0f,0xe3]
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ldmxcsr -485498096(%edx,%eax,4)
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// CHECK: ldmxcsr 485498096(%edx,%eax,4)
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// CHECK: encoding: [0x0f,0xae,0x94,0x82,0xf0,0x1c,0xf0,0x1c]
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ldmxcsr 485498096(%edx,%eax,4)
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// CHECK: ldmxcsr 485498096(%edx)
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// CHECK: encoding: [0x0f,0xae,0x92,0xf0,0x1c,0xf0,0x1c]
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ldmxcsr 485498096(%edx)
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// CHECK: ldmxcsr 485498096
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// CHECK: encoding: [0x0f,0xae,0x15,0xf0,0x1c,0xf0,0x1c]
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ldmxcsr 485498096
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// CHECK: ldmxcsr 64(%edx,%eax)
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// CHECK: encoding: [0x0f,0xae,0x54,0x02,0x40]
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ldmxcsr 64(%edx,%eax)
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// CHECK: ldmxcsr (%edx)
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// CHECK: encoding: [0x0f,0xae,0x12]
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ldmxcsr (%edx)
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// CHECK: stmxcsr -485498096(%edx,%eax,4)
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// CHECK: encoding: [0x0f,0xae,0x9c,0x82,0x10,0xe3,0x0f,0xe3]
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stmxcsr -485498096(%edx,%eax,4)
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// CHECK: stmxcsr 485498096(%edx,%eax,4)
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// CHECK: encoding: [0x0f,0xae,0x9c,0x82,0xf0,0x1c,0xf0,0x1c]
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stmxcsr 485498096(%edx,%eax,4)
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// CHECK: stmxcsr 485498096(%edx)
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// CHECK: encoding: [0x0f,0xae,0x9a,0xf0,0x1c,0xf0,0x1c]
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stmxcsr 485498096(%edx)
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// CHECK: stmxcsr 485498096
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// CHECK: encoding: [0x0f,0xae,0x1d,0xf0,0x1c,0xf0,0x1c]
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stmxcsr 485498096
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// CHECK: stmxcsr 64(%edx,%eax)
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// CHECK: encoding: [0x0f,0xae,0x5c,0x02,0x40]
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stmxcsr 64(%edx,%eax)
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// CHECK: stmxcsr (%edx)
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// CHECK: encoding: [0x0f,0xae,0x1a]
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stmxcsr (%edx)
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