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AsmParser
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[RISCV] Change ConstraintMask in RISCVII enum to be shifted left. NFC
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2021-01-09 20:22:07 -08:00 |
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Disassembler
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[RISCV] Support Zfh half-precision floating-point extension.
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2020-12-03 09:16:33 +08:00 |
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MCTargetDesc
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[RISCV] Remove unused method RISCVInstPrinter::printSImm5Plus1. NFC
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2021-01-04 12:21:35 -08:00 |
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TargetInfo
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llvmbuildectomy - replace llvm-build by plain cmake
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2020-11-13 10:35:24 +01:00 |
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Utils
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[RISCV] Convert most of the information about RVV Pseudos into bits in TSFlags.
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2021-01-10 19:15:45 -08:00 |
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CMakeLists.txt
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[RISCV] Add a pass to remove duplicate VSETVLI instructions in a basic block.
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2020-12-11 10:35:37 -08:00 |
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RISCV.h
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[RISCV] Add a pass to remove duplicate VSETVLI instructions in a basic block.
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2020-12-11 10:35:37 -08:00 |
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RISCV.td
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[RISCV] V does not imply F.
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2020-12-17 10:57:36 +08:00 |
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RISCVAsmPrinter.cpp
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[RISCV] Add -mtune support
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2020-10-16 13:55:08 +08:00 |
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RISCVCallingConv.td
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RISCVCallLowering.cpp
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[GlobalISel] Base implementation for sret demotion.
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2021-01-06 10:30:50 +05:30 |
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RISCVCallLowering.h
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[GlobalISel] Base implementation for sret demotion.
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2021-01-06 10:30:50 +05:30 |
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RISCVCleanupVSETVLI.cpp
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[RISCV] Add a pass to remove duplicate VSETVLI instructions in a basic block.
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2020-12-11 10:35:37 -08:00 |
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RISCVExpandAtomicPseudoInsts.cpp
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RISCVExpandPseudoInsts.cpp
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[RISCV] Define vmclr.m/vmset.m intrinsics.
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2020-12-28 18:57:17 -08:00 |
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RISCVFrameLowering.cpp
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[RISCV] Do not grow the stack a second time when we need to realign the stack
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2021-01-09 16:51:09 +00:00 |
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RISCVFrameLowering.h
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[SVE] Return StackOffset for TargetFrameLowering::getFrameIndexReference.
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2020-11-05 11:02:18 +00:00 |
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RISCVInstrFormats.td
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[RISCV] Convert most of the information about RVV Pseudos into bits in TSFlags.
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2021-01-10 19:15:45 -08:00 |
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RISCVInstrFormatsC.td
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RISCVInstrFormatsV.td
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RISCVInstrInfo.cpp
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[Target] Use llvm::erase_if (NFC)
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2020-12-20 17:43:22 -08:00 |
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RISCVInstrInfo.h
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[RISCV] Don't include CodeGen layer files in MC layer
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2020-11-12 07:45:38 -08:00 |
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RISCVInstrInfo.td
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[RISCV] Move shift ComplexPatterns and custom isel to PatFrags with predicates
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2021-01-05 11:37:48 -08:00 |
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RISCVInstrInfoA.td
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RISCVInstrInfoB.td
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[RISCV] Legalize select when Zbt extension available
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2021-01-12 21:24:38 +00:00 |
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RISCVInstrInfoC.td
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[RISCV] Add support for printing pcrel immediates as absolute addresses in llvm-objdump
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2020-12-04 10:34:12 -08:00 |
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RISCVInstrInfoD.td
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[RISCV][LegalizeDAG] Expand SETO and SETUO comparisons. Teach LegalizeDAG to expand SETUO expansion when UNE isn't legal.
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2020-12-10 09:15:52 -08:00 |
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RISCVInstrInfoF.td
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[RISCV][LegalizeDAG] Expand SETO and SETUO comparisons. Teach LegalizeDAG to expand SETUO expansion when UNE isn't legal.
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2020-12-10 09:15:52 -08:00 |
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RISCVInstrInfoM.td
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[RISCV] Don't remove (and X, 0xffffffff) from inputs when matching RISCVISD::DIVUW/REMUW to 64-bit DIVU/REMU.
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2020-11-26 23:15:41 -08:00 |
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RISCVInstrInfoV.td
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[RISCV] Clear isCodeGenOnly flag on VMSGE(U) pseudo instructions. Remove InstAliases that duplicate the asm strings in the pseudos.
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2021-01-10 23:39:08 -08:00 |
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RISCVInstrInfoVPseudos.td
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[RISCV] Remove '.mask' from vcompress intrinsic name. NFC
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2021-01-12 14:46:16 -08:00 |
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RISCVInstrInfoVSDPatterns.td
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[RISCV] Add scalable vector vselect ISel patterns
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2021-01-11 22:41:34 +00:00 |
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RISCVInstrInfoZfh.td
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[RISCV][LegalizeDAG] Expand SETO and SETUO comparisons. Teach LegalizeDAG to expand SETUO expansion when UNE isn't legal.
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2020-12-10 09:15:52 -08:00 |
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RISCVInstructionSelector.cpp
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RISCVISelDAGToDAG.cpp
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[RISCV] Move shift ComplexPatterns and custom isel to PatFrags with predicates
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2021-01-05 11:37:48 -08:00 |
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RISCVISelDAGToDAG.h
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[RISCV] Move shift ComplexPatterns and custom isel to PatFrags with predicates
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2021-01-05 11:37:48 -08:00 |
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RISCVISelLowering.cpp
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[RISCV] Legalize select when Zbt extension available
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2021-01-12 21:24:38 +00:00 |
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RISCVISelLowering.h
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[RISCV] Add ISel support for RVV vector/scalar forms
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2020-12-23 20:16:18 +00:00 |
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RISCVLegalizerInfo.cpp
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RISCVLegalizerInfo.h
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RISCVMachineFunctionInfo.h
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RISCVMCInstLower.cpp
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[RISCV] Convert most of the information about RVV Pseudos into bits in TSFlags.
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2021-01-10 19:15:45 -08:00 |
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RISCVMergeBaseOffset.cpp
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[RISCV] Support Zfh half-precision floating-point extension.
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2020-12-03 09:16:33 +08:00 |
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RISCVRegisterBankInfo.cpp
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RISCVRegisterBankInfo.h
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RISCVRegisterBanks.td
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RISCVRegisterInfo.cpp
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[RISCV] Define the remaining vector fixed-point arithmetic intrinsics.
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2020-12-20 22:57:07 -08:00 |
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RISCVRegisterInfo.h
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RISCVRegisterInfo.td
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[RISCV] Define the remaining vector fixed-point arithmetic intrinsics.
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2020-12-20 22:57:07 -08:00 |
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RISCVSchedRocket.td
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[RISCV] Fix formatting (NFC)
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2020-09-25 18:15:04 -05:00 |
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RISCVSchedSiFive7.td
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[RISCV] Use the commercial name for scheduling model (NFC)
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2020-10-23 16:33:27 -05:00 |
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RISCVSchedule.td
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[RISCV] Fix formatting (NFC)
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2020-09-25 18:15:04 -05:00 |
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RISCVSubtarget.cpp
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[RISCV] Add -mtune support
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2020-10-16 13:55:08 +08:00 |
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RISCVSubtarget.h
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[RISCV] Support Zfh half-precision floating-point extension.
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2020-12-03 09:16:33 +08:00 |
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RISCVSystemOperands.td
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RISCVTargetMachine.cpp
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[RISCV] Address clang-tidy warnings in RISCVTargetMachine. NFC.
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2020-12-18 21:50:55 +00:00 |
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RISCVTargetMachine.h
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[RISCV] Address clang-tidy warnings in RISCVTargetMachine. NFC.
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2020-12-18 21:50:55 +00:00 |
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RISCVTargetObjectFile.cpp
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RISCVTargetObjectFile.h
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RISCVTargetTransformInfo.cpp
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[ARM][TTI] Prevents constants in a min(max) or max(min) pattern from being hoisted when in a loop
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2020-09-22 11:54:10 +00:00 |
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RISCVTargetTransformInfo.h
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[ARM][TTI] Prevents constants in a min(max) or max(min) pattern from being hoisted when in a loop
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2020-09-22 11:54:10 +00:00 |
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