Matt Arsenault 91343fcbc8 R600/SI: Relax some ordering in tests. ... This will help with enabling misched llvm-svn: 216971		2014-09-02 21:45:50 +00:00
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AArch64	Replace -use-init-array with -use-ctors.	2014-09-02 13:54:53 +00:00
ARM	[ARM] Add Thumb-2 code size optimization regression test for EOR.	2014-09-01 12:59:34 +00:00
CPP
Generic
Hexagon
Inputs
Mips	Replace -use-init-array with -use-ctors.	2014-09-02 13:54:53 +00:00
MSP430	Do not assume the value passed to memset is an i32.	2014-08-29 08:23:53 +00:00
NVPTX	[MachineSink] Use the real post dominator tree	2014-09-01 03:47:25 +00:00
PowerPC	Enable splitting indexing from loads with TargetConstants	2014-09-02 16:05:23 +00:00
R600	R600/SI: Relax some ordering in tests.	2014-09-02 21:45:50 +00:00
SPARC
SystemZ
Thumb	ARM / x86_64 varargs: Don't save regparms in prologue without va_start	2014-08-22 21:59:26 +00:00
Thumb2	ARM / x86_64 varargs: Don't save regparms in prologue without va_start	2014-08-22 21:59:26 +00:00
X86	CodeGen: Handle va_start in the entry block	2014-09-02 18:42:44 +00:00
XCore