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llvm-mirror/test/CodeGen/X86/test-nofold.ll
Andrew Trick e3e67d4a0a Enable MI Sched for x86.
This changes the SelectionDAG scheduling preference to source
order. Soon, the SelectionDAG scheduler can be bypassed saving
a nice chunk of compile time.

Performance differences that result from this change are often a
consequence of register coalescing. The register coalescer is far from
perfect. Bugs can be filed for deficiencies.

On x86 SandyBridge/Haswell, the source order schedule is often
preserved, particularly for small blocks.

Register pressure is generally improved over the SD scheduler's ILP
mode. However, we are still able to handle large blocks that require
latency hiding, unlike the SD scheduler's BURR mode. MI scheduler also
attempts to discover the critical path in single-block loops and
adjust heuristics accordingly.

The MI scheduler relies on the new machine model. This is currently
unimplemented for AVX, so we may not be generating the best code yet.

Unit tests are updated so they don't depend on SD scheduling heuristics.

llvm-svn: 192750
2013-10-15 23:33:07 +00:00

42 lines
913 B
LLVM

; RUN: llc < %s -march=x86 -mcpu=yonah | FileCheck %s
; rdar://5752025
; We want:
; CHECK: movl 4(%esp), %ecx
; CHECK-NEXT: andl $15, %ecx
; CHECK-NEXT: movl $42, %eax
; CHECK-NEXT: cmovel %ecx, %eax
; CHECK-NEXT: ret
;
; We don't want:
; movl 4(%esp), %eax
; movl %eax, %ecx # bad: extra copy
; andl $15, %ecx
; testl $15, %eax # bad: peep obstructed
; movl $42, %eax
; cmovel %ecx, %eax
; ret
;
; We also don't want:
; movl $15, %ecx # bad: larger encoding
; andl 4(%esp), %ecx
; movl $42, %eax
; cmovel %ecx, %eax
; ret
;
; We also don't want:
; movl 4(%esp), %ecx
; andl $15, %ecx
; testl %ecx, %ecx # bad: unnecessary test
; movl $42, %eax
; cmovel %ecx, %eax
; ret
define i32 @t1(i32 %X) nounwind {
entry:
%tmp2 = and i32 %X, 15 ; <i32> [#uses=2]
%tmp4 = icmp eq i32 %tmp2, 0 ; <i1> [#uses=1]
%retval = select i1 %tmp4, i32 %tmp2, i32 42 ; <i32> [#uses=1]
ret i32 %retval
}