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5f91239343
This patch uses the mechanism from D62995 to strengthen the definitions of the reduction intrinsics by letting the scalar result/accumulator type be overloaded from the vector element type. For example: ; The LLVM LangRef specifies that the scalar result must equal the ; vector element type, but this is not checked/enforced by LLVM. declare i32 @llvm.experimental.vector.reduce.or.i32.v4i32(<4 x i32> %a) This patch changes that into: declare i32 @llvm.experimental.vector.reduce.or.v4i32(<4 x i32> %a) Which has the type-constraint more explicit and causes LLVM to check the result type with the vector element type. Reviewers: RKSimon, arsenm, rnk, greened, aemerson Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D62996 llvm-svn: 363240
70 lines
2.4 KiB
LLVM
70 lines
2.4 KiB
LLVM
; RUN: llc < %s -mtriple=aarch64-eabi -aarch64-neon-syntax=generic | FileCheck %s
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; Function Attrs: nounwind readnone
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declare i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64>)
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declare i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32>)
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declare i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16>)
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declare i8 @llvm.experimental.vector.reduce.add.v16i8(<16 x i8>)
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define i8 @add_B(<16 x i8>* %arr) {
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; CHECK-LABEL: add_B
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; CHECK: addv {{b[0-9]+}}, {{v[0-9]+}}.16b
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%bin.rdx = load <16 x i8>, <16 x i8>* %arr
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%r = call i8 @llvm.experimental.vector.reduce.add.v16i8(<16 x i8> %bin.rdx)
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ret i8 %r
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}
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define i16 @add_H(<8 x i16>* %arr) {
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; CHECK-LABEL: add_H
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; CHECK: addv {{h[0-9]+}}, {{v[0-9]+}}.8h
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%bin.rdx = load <8 x i16>, <8 x i16>* %arr
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%r = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> %bin.rdx)
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ret i16 %r
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}
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define i32 @add_S( <4 x i32>* %arr) {
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; CHECK-LABEL: add_S
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; CHECK: addv {{s[0-9]+}}, {{v[0-9]+}}.4s
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%bin.rdx = load <4 x i32>, <4 x i32>* %arr
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%r = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %bin.rdx)
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ret i32 %r
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}
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define i64 @add_D(<2 x i64>* %arr) {
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; CHECK-LABEL: add_D
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; CHECK-NOT: addv
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%bin.rdx = load <2 x i64>, <2 x i64>* %arr
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%r = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> %bin.rdx)
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ret i64 %r
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}
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declare i32 @llvm.experimental.vector.reduce.add.v8i32(<8 x i32>)
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define i32 @oversized_ADDV_256(i8* noalias nocapture readonly %arg1, i8* noalias nocapture readonly %arg2) {
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; CHECK-LABEL: oversized_ADDV_256
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; CHECK: addv {{s[0-9]+}}, {{v[0-9]+}}.4s
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entry:
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%0 = bitcast i8* %arg1 to <8 x i8>*
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%1 = load <8 x i8>, <8 x i8>* %0, align 1
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%2 = zext <8 x i8> %1 to <8 x i32>
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%3 = bitcast i8* %arg2 to <8 x i8>*
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%4 = load <8 x i8>, <8 x i8>* %3, align 1
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%5 = zext <8 x i8> %4 to <8 x i32>
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%6 = sub nsw <8 x i32> %2, %5
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%7 = icmp slt <8 x i32> %6, zeroinitializer
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%8 = sub nsw <8 x i32> zeroinitializer, %6
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%9 = select <8 x i1> %7, <8 x i32> %8, <8 x i32> %6
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%r = call i32 @llvm.experimental.vector.reduce.add.v8i32(<8 x i32> %9)
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ret i32 %r
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}
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declare i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32>)
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define i32 @oversized_ADDV_512(<16 x i32>* %arr) {
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; CHECK-LABEL: oversized_ADDV_512
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; CHECK: addv {{s[0-9]+}}, {{v[0-9]+}}.4s
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%bin.rdx = load <16 x i32>, <16 x i32>* %arr
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%r = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %bin.rdx)
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ret i32 %r
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}
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