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b2a4fe0946
This patch follows some ideas from r352866 to optimize the floating point materialization even further. It changes isFPImmLegal to considere up to 2 mov instruction or up to 5 in case subtarget has fused literals. The rationale is the cost is the same for mov+fmov vs. adrp+ldr; but the mov+fmov sequence is always better because of the reduced d-cache pressure. The timings are still the same if you consider movw+movk+fmov vs. adrp+ldr will be fused (although one instruction longer). Reviewers: efriedma Differential Revision: https://reviews.llvm.org/D58460 llvm-svn: 356390
32 lines
741 B
LLVM
32 lines
741 B
LLVM
; RUN: llc < %s -mtriple=arm64-apple-darwin | FileCheck %s
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; CHECK: literal8
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; CHECK: .quad 4614256656552045848
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define double @foo() {
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; CHECK: _foo:
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; CHECK: adrp x[[REG:[0-9]+]], lCPI0_0@PAGE
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; CHECK: ldr d0, [x[[REG]], lCPI0_0@PAGEOFF]
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; CHECK-NEXT: ret
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ret double 0x400921FB54442D18
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}
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define float @bar() {
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; CHECK: _bar:
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; CHECK: mov [[REG:w[0-9]+]], #4059
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; CHECK: movk [[REG]], #16457, lsl #16
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; CHECK: fmov s0, [[REG]]
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; CHECK-NEXT: ret
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ret float 0x400921FB60000000
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}
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; CHECK: literal16
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; CHECK: .quad 0
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; CHECK: .quad 0
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define fp128 @baz() {
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; CHECK: _baz:
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; CHECK: adrp x[[REG:[0-9]+]], lCPI2_0@PAGE
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; CHECK: ldr q0, [x[[REG]], lCPI2_0@PAGEOFF]
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; CHECK-NEXT: ret
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ret fp128 0xL00000000000000000000000000000000
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}
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