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https://github.com/RPCS3/llvm-mirror.git
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bc7846dad0
This adds GlobalISel equivalents for the following from AArch64InstrFormats: - arith_shifted_reg32 - arith_shifted_reg64 And partial support for - logical_shifted_reg32 - logical_shifted_reg32 The only thing missing for the logical cases is support for rotates. Other than the missing support, the transformation is identical for the arithmetic shifted register and the logical shifted register. Lots of tests here: - Add select-arith-shifted-reg.mir to show that we correctly select add and sub instructions which use this pattern. - Add select-logical-shifted-reg.mir to cover patterns which are not shared between the arithmetic and logical cases. - Update addsub-shifted.ll to show that we correctly fold shifts into adds/subs. - Update eon.ll to show that we can select the eon instruction by folding xors. Differential Revision: https://reviews.llvm.org/D66163 llvm-svn: 369460
33 lines
770 B
LLVM
33 lines
770 B
LLVM
; RUN: llc -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s
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; RUN: llc %s -pass-remarks-missed=gisel* -mtriple=aarch64-none-linux-gnu -global-isel -o - 2>&1 | FileCheck %s
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; CHECK-NOT: remark
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; Check that the eon instruction is generated instead of eor,movn
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define i64 @test1(i64 %a, i64 %b, i64 %c) {
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; CHECK-LABEL: test1:
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; CHECK: eon
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; CHECK: ret
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entry:
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%shl = shl i64 %b, 4
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%neg = xor i64 %a, -1
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%xor = xor i64 %shl, %neg
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ret i64 %xor
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}
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; Same check with mutliple uses of %neg
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define i64 @test2(i64 %a, i64 %b, i64 %c) {
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; CHECK-LABEL: test2:
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; CHECK: eon
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; CHECK: eon
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; CHECK: lsl
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; CHECK: ret
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entry:
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%shl = shl i64 %b, 4
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%neg = xor i64 %shl, -1
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%xor = xor i64 %neg, %a
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%xor1 = xor i64 %c, %neg
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%shl2 = shl i64 %xor, %xor1
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ret i64 %shl2
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}
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