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Most immediates are printed in Aarch64InstPrinter using 'formatImm' macro, but not all of them. Implementation contains following rules: - floating point immediates are always printed as decimal - signed integer immediates are printed depends on flag settings (for negative values 'formatImm' macro prints the value as i.e -0x01 which may be convenient when imm is an address or offset) - logical immediates are always printed as hex - the 64-bit immediate for advSIMD, encoded in "a🅱️c:d:e:f:g:h" is always printed as hex - the 64-bit immedaite in exception generation instructions like: brk, dcps1, dcps2, dcps3, hlt, hvc, smc, svc is always printed as hex - the rest of immediates is printed depends on availability of -print-imm-hex Signed-off-by: Maciej Gabka <maciej.gabka@arm.com> Signed-off-by: Paul Osmialowski <pawel.osmialowski@arm.com> Differential Revision: http://reviews.llvm.org/D16929 llvm-svn: 269446
90 lines
2.9 KiB
LLVM
90 lines
2.9 KiB
LLVM
; RUN: llc < %s -asm-verbose=false -mtriple=aarch64-none-eabi | FileCheck %s
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; Test pattern (v4f16 (AArch64NvCast (v2i32 FPR64:$src)))
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define void @nvcast_v2i32(<4 x half>* %a) #0 {
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; CHECK-LABEL: nvcast_v2i32:
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; CHECK-NEXT: movi v[[REG:[0-9]+]].2s, #171, lsl #16
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; CHECK-NEXT: str d[[REG]], [x0]
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; CHECK-NEXT: ret
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store volatile <4 x half> <half 0xH0000, half 0xH00AB, half 0xH0000, half 0xH00AB>, <4 x half>* %a
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ret void
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}
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; Test pattern (v4f16 (AArch64NvCast (v4i16 FPR64:$src)))
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define void @nvcast_v4i16(<4 x half>* %a) #0 {
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; CHECK-LABEL: nvcast_v4i16:
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; CHECK-NEXT: movi v[[REG:[0-9]+]].4h, #171
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; CHECK-NEXT: str d[[REG]], [x0]
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; CHECK-NEXT: ret
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store volatile <4 x half> <half 0xH00AB, half 0xH00AB, half 0xH00AB, half 0xH00AB>, <4 x half>* %a
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ret void
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}
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; Test pattern (v4f16 (AArch64NvCast (v8i8 FPR64:$src)))
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define void @nvcast_v8i8(<4 x half>* %a) #0 {
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; CHECK-LABEL: nvcast_v8i8:
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; CHECK-NEXT: movi v[[REG:[0-9]+]].8b, #171
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; CHECK-NEXT: str d[[REG]], [x0]
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; CHECK-NEXT: ret
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store volatile <4 x half> <half 0xHABAB, half 0xHABAB, half 0xHABAB, half 0xHABAB>, <4 x half>* %a
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ret void
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}
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; Test pattern (v4f16 (AArch64NvCast (f64 FPR64:$src)))
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define void @nvcast_f64(<4 x half>* %a) #0 {
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; CHECK-LABEL: nvcast_f64:
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; CHECK-NEXT: movi d[[REG:[0-9]+]], #0000000000000000
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; CHECK-NEXT: str d[[REG]], [x0]
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; CHECK-NEXT: ret
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store volatile <4 x half> zeroinitializer, <4 x half>* %a
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ret void
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}
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; Test pattern (v8f16 (AArch64NvCast (v4i32 FPR128:$src)))
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define void @nvcast_v4i32(<8 x half>* %a) #0 {
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; CHECK-LABEL: nvcast_v4i32:
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; CHECK-NEXT: movi v[[REG:[0-9]+]].4s, #171, lsl #16
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; CHECK-NEXT: str q[[REG]], [x0]
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; CHECK-NEXT: ret
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store volatile <8 x half> <half 0xH0000, half 0xH00AB, half 0xH0000, half 0xH00AB, half 0xH0000, half 0xH00AB, half 0xH0000, half 0xH00AB>, <8 x half>* %a
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ret void
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}
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; Test pattern (v8f16 (AArch64NvCast (v8i16 FPR128:$src)))
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define void @nvcast_v8i16(<8 x half>* %a) #0 {
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; CHECK-LABEL: nvcast_v8i16:
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; CHECK-NEXT: movi v[[REG:[0-9]+]].8h, #171
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; CHECK-NEXT: str q[[REG]], [x0]
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; CHECK-NEXT: ret
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store volatile <8 x half> <half 0xH00AB, half 0xH00AB, half 0xH00AB, half 0xH00AB, half 0xH00AB, half 0xH00AB, half 0xH00AB, half 0xH00AB>, <8 x half>* %a
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ret void
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}
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; Test pattern (v8f16 (AArch64NvCast (v16i8 FPR128:$src)))
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define void @nvcast_v16i8(<8 x half>* %a) #0 {
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; CHECK-LABEL: nvcast_v16i8:
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; CHECK-NEXT: movi v[[REG:[0-9]+]].16b, #171
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; CHECK-NEXT: str q[[REG]], [x0]
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; CHECK-NEXT: ret
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store volatile <8 x half> <half 0xHABAB, half 0xHABAB, half 0xHABAB, half 0xHABAB, half 0xHABAB, half 0xHABAB, half 0xHABAB, half 0xHABAB>, <8 x half>* %a
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ret void
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}
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; Test pattern (v8f16 (AArch64NvCast (v2i64 FPR128:$src)))
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define void @nvcast_v2i64(<8 x half>* %a) #0 {
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; CHECK-LABEL: nvcast_v2i64:
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; CHECK-NEXT: movi v[[REG:[0-9]+]].2d, #0000000000000000
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; CHECK-NEXT: str q[[REG]], [x0]
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; CHECK-NEXT: ret
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store volatile <8 x half> zeroinitializer, <8 x half>* %a
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ret void
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}
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attributes #0 = { nounwind }
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