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b87a61b44f
This matches the ARM behavior. In both cases, the register is part of the optional Performance Monitors extension, so, add the feature, and enable it for the A-class processors we support. Differential Revision: http://reviews.llvm.org/D12425 llvm-svn: 246555
16 lines
578 B
LLVM
16 lines
578 B
LLVM
; RUN: llc -mtriple=aarch64-unknown-unknown -asm-verbose=false < %s |\
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; RUN: FileCheck %s --check-prefix=CHECK --check-prefix=PERFMON
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; RUN: llc -mtriple=aarch64-unknown-unknown -mattr=-perfmon -asm-verbose=false < %s |\
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; RUN: FileCheck %s --check-prefix=CHECK --check-prefix=NOPERFMON
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define i64 @test_readcyclecounter() nounwind {
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; CHECK-LABEL: test_readcyclecounter:
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; PERFMON-NEXT: mrs x0, PMCCNTR_EL0
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; NOPERFMON-NEXT: mov x0, xzr
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; CHECK-NEXT: ret
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%tmp0 = call i64 @llvm.readcyclecounter()
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ret i64 %tmp0
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}
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declare i64 @llvm.readcyclecounter()
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