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95037fa9f6
Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
70 lines
2.2 KiB
LLVM
70 lines
2.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32IFD %s
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; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64IFD %s
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define double @func(double %d, i32 %n) nounwind {
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; RV32IFD-LABEL: func:
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; RV32IFD: # %bb.0: # %entry
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; RV32IFD-NEXT: addi sp, sp, -32
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; RV32IFD-NEXT: sw ra, 28(sp)
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; RV32IFD-NEXT: sw a0, 16(sp)
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; RV32IFD-NEXT: sw a1, 20(sp)
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; RV32IFD-NEXT: fld ft0, 16(sp)
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; RV32IFD-NEXT: beqz a2, .LBB0_2
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; RV32IFD-NEXT: # %bb.1: # %if.else
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; RV32IFD-NEXT: addi a2, a2, -1
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; RV32IFD-NEXT: fsd ft0, 16(sp)
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; RV32IFD-NEXT: lw a0, 16(sp)
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; RV32IFD-NEXT: lw a1, 20(sp)
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; RV32IFD-NEXT: fsd ft0, 8(sp)
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; RV32IFD-NEXT: call func
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; RV32IFD-NEXT: sw a0, 16(sp)
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; RV32IFD-NEXT: sw a1, 20(sp)
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; RV32IFD-NEXT: fld ft0, 16(sp)
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; RV32IFD-NEXT: fld ft1, 8(sp)
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; RV32IFD-NEXT: fadd.d ft0, ft0, ft1
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; RV32IFD-NEXT: .LBB0_2: # %return
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; RV32IFD-NEXT: fsd ft0, 16(sp)
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; RV32IFD-NEXT: lw a0, 16(sp)
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; RV32IFD-NEXT: lw a1, 20(sp)
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; RV32IFD-NEXT: lw ra, 28(sp)
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; RV32IFD-NEXT: addi sp, sp, 32
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; RV32IFD-NEXT: ret
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;
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; RV64IFD-LABEL: func:
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; RV64IFD: # %bb.0: # %entry
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; RV64IFD-NEXT: addi sp, sp, -16
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; RV64IFD-NEXT: sd ra, 8(sp)
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; RV64IFD-NEXT: slli a2, a1, 32
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; RV64IFD-NEXT: srli a2, a2, 32
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; RV64IFD-NEXT: fmv.d.x ft0, a0
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; RV64IFD-NEXT: beqz a2, .LBB0_2
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; RV64IFD-NEXT: # %bb.1: # %if.else
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; RV64IFD-NEXT: addi a1, a1, -1
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; RV64IFD-NEXT: fmv.x.d a0, ft0
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; RV64IFD-NEXT: fsd ft0, 0(sp)
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; RV64IFD-NEXT: call func
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; RV64IFD-NEXT: fmv.d.x ft0, a0
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; RV64IFD-NEXT: fld ft1, 0(sp)
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; RV64IFD-NEXT: fadd.d ft0, ft0, ft1
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; RV64IFD-NEXT: .LBB0_2: # %return
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; RV64IFD-NEXT: fmv.x.d a0, ft0
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; RV64IFD-NEXT: ld ra, 8(sp)
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; RV64IFD-NEXT: addi sp, sp, 16
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; RV64IFD-NEXT: ret
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entry:
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%cmp = icmp eq i32 %n, 0
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br i1 %cmp, label %return, label %if.else
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if.else:
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%sub = add i32 %n, -1
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%call = tail call double @func(double %d, i32 %sub)
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%add = fadd double %call, %d
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ret double %add
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return:
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ret double %d
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}
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