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95037fa9f6
Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
98 lines
3.0 KiB
LLVM
98 lines
3.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s | FileCheck %s
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define signext i32 @addw(i32 signext %s, i32 signext %n, i32 signext %k) nounwind {
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; CHECK-LABEL: addw:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: bge a0, a1, .LBB0_2
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; CHECK-NEXT: # %bb.1: # %for.body.preheader
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; CHECK-NEXT: not a2, a0
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; CHECK-NEXT: add a2, a2, a1
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; CHECK-NEXT: addi a3, a0, 1
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; CHECK-NEXT: mul a3, a2, a3
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; CHECK-NEXT: slli a2, a2, 32
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; CHECK-NEXT: srli a2, a2, 32
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; CHECK-NEXT: sub a1, a1, a0
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; CHECK-NEXT: addi a1, a1, -2
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; CHECK-NEXT: slli a1, a1, 32
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; CHECK-NEXT: srli a1, a1, 32
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; CHECK-NEXT: mul a1, a2, a1
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; CHECK-NEXT: srli a1, a1, 1
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; CHECK-NEXT: add a0, a3, a0
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; CHECK-NEXT: addw a0, a0, a1
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB0_2:
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; CHECK-NEXT: mv a0, zero
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; CHECK-NEXT: ret
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entry:
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%cmp6 = icmp slt i32 %s, %n
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br i1 %cmp6, label %for.body.preheader, label %for.cond.cleanup
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for.body.preheader: ; preds = %entry
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%0 = xor i32 %s, -1
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%1 = add i32 %0, %n
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%2 = add i32 %s, 1
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%3 = mul i32 %1, %2
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%4 = zext i32 %1 to i33
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%5 = add i32 %n, -2
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%6 = sub i32 %5, %s
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%7 = zext i32 %6 to i33
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%8 = mul i33 %4, %7
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%9 = lshr i33 %8, 1
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%10 = trunc i33 %9 to i32
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%11 = add i32 %3, %s
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%12 = add i32 %11, %10
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br label %for.cond.cleanup
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for.cond.cleanup: ; preds = %for.body.preheader, %entry
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%sum.0.lcssa = phi i32 [ 0, %entry ], [ %12, %for.body.preheader ]
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ret i32 %sum.0.lcssa
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}
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define signext i32 @subw(i32 signext %s, i32 signext %n, i32 signext %k) nounwind {
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; CHECK-LABEL: subw:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: bge a0, a1, .LBB1_2
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; CHECK-NEXT: # %bb.1: # %for.body.preheader
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; CHECK-NEXT: not a2, a0
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; CHECK-NEXT: add a3, a2, a1
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; CHECK-NEXT: mul a2, a3, a2
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; CHECK-NEXT: slli a3, a3, 32
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; CHECK-NEXT: srli a3, a3, 32
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; CHECK-NEXT: sub a1, a1, a0
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; CHECK-NEXT: addi a1, a1, -2
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; CHECK-NEXT: slli a1, a1, 32
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; CHECK-NEXT: srli a1, a1, 32
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; CHECK-NEXT: mul a1, a3, a1
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; CHECK-NEXT: srli a1, a1, 1
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; CHECK-NEXT: sub a0, a2, a0
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; CHECK-NEXT: subw a0, a0, a1
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB1_2:
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; CHECK-NEXT: mv a0, zero
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; CHECK-NEXT: ret
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entry:
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%cmp6 = icmp slt i32 %s, %n
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br i1 %cmp6, label %for.body.preheader, label %for.cond.cleanup
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for.body.preheader: ; preds = %entry
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%0 = xor i32 %s, -1
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%1 = add i32 %0, %n
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%2 = xor i32 %s, -1
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%3 = mul i32 %1, %2
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%4 = zext i32 %1 to i33
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%5 = add i32 %n, -2
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%6 = sub i32 %5, %s
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%7 = zext i32 %6 to i33
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%8 = mul i33 %4, %7
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%9 = lshr i33 %8, 1
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%10 = trunc i33 %9 to i32
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%11 = sub i32 %3, %s
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%12 = sub i32 %11, %10
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br label %for.cond.cleanup
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for.cond.cleanup: ; preds = %for.body.preheader, %entry
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%sum.0.lcssa = phi i32 [ 0, %entry ], [ %12, %for.body.preheader ]
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ret i32 %sum.0.lcssa
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}
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