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mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-22 20:43:44 +02:00
llvm-mirror/test/CodeGen
2016-07-22 07:18:33 +00:00
..
AArch64 [AArch64][Inline-Asm] Return the 32-bit floating point register class 2016-07-21 21:39:05 +00:00
AMDGPU Revert "Invariant start/end intrinsics overloaded for address space" 2016-07-21 19:06:28 +00:00
ARM [ARM] Skip inline asm memory operands in DAGToDAGISel 2016-07-20 09:48:24 +00:00
BPF
Generic Move mempcpy_call.ll to X86 subdirectory 2016-07-13 18:28:45 +00:00
Hexagon [Hexagon] Handle returning small structures by value 2016-07-18 17:30:41 +00:00
Inputs
Lanai [lanai] Use peephole optimizer to generate more conditional ALU operations. 2016-07-07 23:36:04 +00:00
Mips [mips][microMIPS] Implement SLT, SLTI, SLTIU, SLTU microMIPS32r6 instructions 2016-07-22 07:18:33 +00:00
MIR [MIRTesting] Abort when failing to parse a function. 2016-07-21 22:25:57 +00:00
MSP430
NVPTX [NVPTX] Enable the load-store vectorizer on nvptx. 2016-07-20 22:11:36 +00:00
PowerPC Revert "RegScavenging: Add scavengeRegisterBackwards()" 2016-07-20 00:21:32 +00:00
SPARC VirtRegMap: Replace some identity copies with KILL instructions. 2016-07-09 00:19:07 +00:00
SystemZ Revert "RegScavenging: Add scavengeRegisterBackwards()" 2016-07-20 00:21:32 +00:00
Thumb Revert "RegScavenging: Add scavengeRegisterBackwards()" 2016-07-20 00:21:32 +00:00
Thumb2 [Thumb] Reapply r272251 with a fix for PR28348 (mk 2) 2016-07-05 12:37:13 +00:00
WebAssembly
WinEH revert http://reviews.llvm.org/D21101 2016-06-30 17:52:24 +00:00
X86 [AVX512] Add ExeDomain to vector extend and truncate instructions. 2016-07-22 05:46:44 +00:00
XCore IR: Introduce Module::global_objects(). 2016-06-22 20:29:42 +00:00