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bd0d64e160
Summary: The work item intrinsics are not available for the shader calling conventions. And even if we did hook them up most shader stages haves some extra restrictions on the amount of available LDS. Reviewers: tstellarAMD, arsenm Subscribers: nhaehnle, arsenm, llvm-commits, kzhuravl Differential Revision: https://reviews.llvm.org/D20728 llvm-svn: 275779
30 lines
1.5 KiB
LLVM
30 lines
1.5 KiB
LLVM
; RUN: opt -S -mtriple=amdgcn-unknown-unknown -amdgpu-promote-alloca < %s | FileCheck -check-prefix=IR %s
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; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=ASM %s
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; IR-LABEL: define amdgpu_vs void @promote_alloca_shaders(i32 addrspace(1)* inreg %out, i32 addrspace(1)* inreg %in) #0 {
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; IR: alloca [5 x i32]
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; ASM-LABEL: {{^}}promote_alloca_shaders:
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; ASM: ; LDSByteSize: 0 bytes/workgroup (compile time only)
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define amdgpu_vs void @promote_alloca_shaders(i32 addrspace(1)* inreg %out, i32 addrspace(1)* inreg %in) #0 {
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entry:
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%stack = alloca [5 x i32], align 4
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%tmp0 = load i32, i32 addrspace(1)* %in, align 4
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%arrayidx1 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %tmp0
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store i32 4, i32* %arrayidx1, align 4
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%arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1
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%tmp1 = load i32, i32 addrspace(1)* %arrayidx2, align 4
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%arrayidx3 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %tmp1
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store i32 5, i32* %arrayidx3, align 4
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%arrayidx4 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 0
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%tmp2 = load i32, i32* %arrayidx4, align 4
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store i32 %tmp2, i32 addrspace(1)* %out, align 4
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%arrayidx5 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 1
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%tmp3 = load i32, i32* %arrayidx5
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%arrayidx6 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 1
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store i32 %tmp3, i32 addrspace(1)* %arrayidx6
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ret void
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}
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attributes #0 = { nounwind "amdgpu-max-work-group-size"="64" }
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