mirror of
https://github.com/RPCS3/llvm-mirror.git
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7b7d569297
Summary: A lot of the pseudo instructions are required because LLVM assumes that all integers of the same size as the pointer size are legal. This means that it will not currently expand 16-bit instructions to their 8-bit variants because it thinks 16-bit types are legal for the operations. This also adds all of the CodeGen tests that required the pass to run. Reviewers: arsenm, kparzysz Subscribers: wdng, mgorny, modocache, llvm-commits Differential Revision: https://reviews.llvm.org/D26577 llvm-svn: 287162
149 lines
2.7 KiB
LLVM
149 lines
2.7 KiB
LLVM
; RUN: llc < %s -march=avr | FileCheck %s
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declare void @f1(i8)
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declare void @f2(i8)
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define void @cmp8(i8 %a, i8 %b) {
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; CHECK-LABEL: cmp8:
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; CHECK: cp
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; CHECK-NOT: cpc
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%cmp = icmp eq i8 %a, %b
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br i1 %cmp, label %if.then, label %if.else
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if.then:
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tail call void @f1(i8 %a)
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br label %if.end
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if.else:
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tail call void @f2(i8 %b)
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br label %if.end
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if.end:
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ret void
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}
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declare void @f3(i16)
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declare void @f4(i16)
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define void @cmp16(i16 %a, i16 %b) {
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; CHECK-LABEL: cmp16:
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; CHECK: cp
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; CHECK-NEXT: cpc
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%cmp = icmp eq i16 %a, %b
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br i1 %cmp, label %if.then, label %if.else
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if.then:
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tail call void @f3(i16 %a)
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br label %if.end
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if.else:
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tail call void @f4(i16 %b)
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br label %if.end
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if.end:
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ret void
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}
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declare void @f5(i32)
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declare void @f6(i32)
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define void @cmp32(i32 %a, i32 %b) {
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; CHECK-LABEL: cmp32:
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; CHECK: cp
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; CHECK-NEXT: cpc
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; CHECK-NEXT: cpc
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; CHECK-NEXT: cpc
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%cmp = icmp eq i32 %a, %b
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br i1 %cmp, label %if.then, label %if.else
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if.then:
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tail call void @f5(i32 %a)
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br label %if.end
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if.else:
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tail call void @f6(i32 %b)
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br label %if.end
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if.end:
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ret void
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}
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declare void @f7(i64)
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declare void @f8(i64)
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define void @cmp64(i64 %a, i64 %b) {
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; CHECK-LABEL: cmp64:
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; CHECK: cp
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; CHECK-NEXT: cpc
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; CHECK-NEXT: cpc
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; CHECK-NEXT: cpc
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; CHECK-NEXT: cpc
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; CHECK-NEXT: cpc
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; CHECK-NEXT: cpc
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; CHECK-NEXT: cpc
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%cmp = icmp eq i64 %a, %b
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br i1 %cmp, label %if.then, label %if.else
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if.then:
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tail call void @f7(i64 %a)
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br label %if.end
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if.else:
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tail call void @f8(i64 %b)
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br label %if.end
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if.end:
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ret void
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}
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declare void @f9()
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declare void @f10()
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define void @tst8(i8 %a) {
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; CHECK-LABEL: tst8:
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; CHECK: tst r24
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; CHECK-NEXT: brmi
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%cmp = icmp sgt i8 %a, -1
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br i1 %cmp, label %if.then, label %if.else
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if.then:
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tail call void @f9()
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br label %if.end
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if.else:
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tail call void @f10()
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br label %if.end
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if.end:
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ret void
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}
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define void @tst16(i16 %a) {
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; CHECK-LABEL: tst16:
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; CHECK: tst r25
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; CHECK-NEXT: brmi
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%cmp = icmp sgt i16 %a, -1
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br i1 %cmp, label %if.then, label %if.else
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if.then:
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tail call void @f9()
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br label %if.end
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if.else:
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tail call void @f10()
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br label %if.end
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if.end:
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ret void
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}
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define void @tst32(i32 %a) {
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; CHECK-LABEL: tst32:
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; CHECK: tst r25
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; CHECK-NEXT: brmi
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%cmp = icmp sgt i32 %a, -1
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br i1 %cmp, label %if.then, label %if.else
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if.then:
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tail call void @f9()
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br label %if.end
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if.else:
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tail call void @f10()
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br label %if.end
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if.end:
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ret void
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}
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define void @tst64(i64 %a) {
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; CHECK-LABEL: tst64:
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; CHECK: tst r25
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; CHECK-NEXT: brmi
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%cmp = icmp sgt i64 %a, -1
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br i1 %cmp, label %if.then, label %if.else
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if.then:
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tail call void @f9()
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br label %if.end
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if.else:
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tail call void @f10()
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br label %if.end
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if.end:
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ret void
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}
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