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2d034feb0d
Summary: Before this change, callee-save registers would be rounded up to even pairs of GPRs and FPRs. This change eliminates these extra padding load/stores, though it does keep the stack allocation the same size unless both the GPR and FPR sets have an odd size, in which case one full pair stack slot (16 bytes) is saved. This optimization cannot currently be done for MachO targets since they rely on a fast-path .debug_frame equivalent that can only encode callee-save registers as pairs. Reviewers: t.p.northover, rengolin, mcrosier, jmolloy Subscribers: aemerson, rengolin, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D17000 llvm-svn: 260689
171 lines
4.7 KiB
LLVM
171 lines
4.7 KiB
LLVM
; RUN: llc -mtriple=aarch64-linux-gnu -disable-post-ra -verify-machineinstrs -o - %s | FileCheck %s --check-prefix=CHECK
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; RUN: llc -mtriple=arm64-apple-ios -disable-post-ra -verify-machineinstrs -o - %s | FileCheck %s --check-prefix=CHECK-MACHO
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; RUN: llc -mtriple=aarch64-none-linux-gnu -disable-post-ra -mattr=-fp-armv8 -verify-machineinstrs < %s | FileCheck --check-prefix=CHECK-NOFP-ARM64 %s
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declare void @use_addr(i8*)
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define void @test_simple_alloca(i64 %n) {
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; CHECK-LABEL: test_simple_alloca:
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%buf = alloca i8, i64 %n
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; Make sure we align the stack change to 16 bytes:
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; CHECK: {{mov|add}} x29
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; CHECK: mov [[TMP:x[0-9]+]], sp
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; CHECK: add [[SPDELTA_TMP:x[0-9]+]], x0, #15
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; CHECK: and [[SPDELTA:x[0-9]+]], [[SPDELTA_TMP]], #0xfffffffffffffff0
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; Make sure we change SP. It would be surprising if anything but x0 were used
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; for the final sp, but it could be if it was then moved into x0.
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; CHECK: sub [[NEWSP:x[0-9]+]], [[TMP]], [[SPDELTA]]
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; CHECK: mov sp, [[NEWSP]]
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call void @use_addr(i8* %buf)
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; CHECK: bl use_addr
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ret void
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; Make sure epilogue restores sp from fp
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; CHECK: {{sub|mov}} sp, x29
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; CHECK: ret
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}
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declare void @use_addr_loc(i8*, i64*)
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define i64 @test_alloca_with_local(i64 %n) {
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; CHECK-LABEL: test_alloca_with_local:
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; CHECK-DAG: sub sp, sp, [[LOCAL_STACK:#[0-9]+]]
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; CHECK-DAG: {{mov|add}} x29, sp
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%loc = alloca i64
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%buf = alloca i8, i64 %n
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; Make sure we align the stack change to 16 bytes:
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; CHECK: mov [[TMP:x[0-9]+]], sp
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; CHECK: add [[SPDELTA_TMP:x[0-9]+]], x0, #15
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; CHECK: and [[SPDELTA:x[0-9]+]], [[SPDELTA_TMP]], #0xfffffffffffffff0
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; Make sure we change SP. It would be surprising if anything but x0 were used
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; for the final sp, but it could be if it was then moved into x0.
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; CHECK: sub [[NEWSP:x[0-9]+]], [[TMP]], [[SPDELTA]]
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; CHECK: mov sp, [[NEWSP]]
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; CHECK: sub {{x[0-9]+}}, x29, #[[LOC_FROM_FP:[0-9]+]]
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call void @use_addr_loc(i8* %buf, i64* %loc)
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; CHECK: bl use_addr
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%val = load i64, i64* %loc
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; CHECK: ldur x0, [x29, #-[[LOC_FROM_FP]]]
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ret i64 %val
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; Make sure epilogue restores sp from fp
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; CHECK: {{sub|mov}} sp, x29
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; CHECK: ret
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}
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define void @test_variadic_alloca(i64 %n, ...) {
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; CHECK-LABEL: test_variadic_alloca:
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; [...]
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; CHECK-NOFP-AARCH64: sub sp, sp, #80
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; CHECK-NOFP-AARCH64: stp x29, x30, [sp, #64]
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; CHECK-NOFP-AARCH64: add x29, sp, #64
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; CHECK-NOFP-AARCH64: sub [[TMP:x[0-9]+]], x29, #64
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; CHECK-NOFP-AARCH64: add x8, [[TMP]], #0
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; CHECK: stp x29, x30, [sp, #-16]!
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; CHECK: mov x29, sp
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; CHECK: sub sp, sp, #192
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; CHECK: stp q6, q7, [x29, #-96]
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; [...]
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; CHECK: stp q0, q1, [x29, #-192]
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; CHECK: stp x6, x7, [x29, #-16]
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; [...]
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; CHECK: stp x2, x3, [x29, #-48]
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; CHECK-NOFP-ARM64: stp x29, x30, [sp, #-16]!
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; CHECK-NOFP-ARM64: mov x29, sp
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; CHECK-NOFP-ARM64: sub sp, sp, #64
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; CHECK-NOFP-ARM64: stp x6, x7, [x29, #-16]
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; [...]
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; CHECK-NOFP-ARM64: stp x4, x5, [x29, #-32]
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; [...]
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; CHECK-NOFP-ARM64: stp x2, x3, [x29, #-48]
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; [...]
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; CHECK-NOFP-ARM64: mov x8, sp
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%addr = alloca i8, i64 %n
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call void @use_addr(i8* %addr)
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; CHECK: bl use_addr
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ret void
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; CHECK-NOFP-AARCH64: sub sp, x29, #64
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; CHECK-NOFP-AARCH64: ldp x29, x30, [sp, #64]
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; CHECK-NOFP-AARCH64: add sp, sp, #80
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; CHECK-NOFP-ARM64: mov sp, x29
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; CHECK-NOFP-ARM64: ldp x29, x30, [sp], #16
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}
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define void @test_alloca_large_frame(i64 %n) {
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; CHECK-LABEL: test_alloca_large_frame:
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; CHECK-MACHO-LABEL: test_alloca_large_frame:
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; CHECK: stp x28, x19, [sp, #-32]!
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; CHECK: stp x29, x30, [sp, #16]
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; CHECK: add x29, sp, #16
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; CHECK: sub sp, sp, #1953, lsl #12
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; CHECK: sub sp, sp, #512
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; CHECK-MACHO: stp x20, x19, [sp, #-32]!
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; CHECK-MACHO: stp x29, x30, [sp, #16]
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; CHECK-MACHO: add x29, sp, #16
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; CHECK-MACHO: sub sp, sp, #1953, lsl #12
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; CHECK-MACHO: sub sp, sp, #512
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%addr1 = alloca i8, i64 %n
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%addr2 = alloca i64, i64 1000000
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call void @use_addr_loc(i8* %addr1, i64* %addr2)
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ret void
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; CHECK: sub sp, x29, #16
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; CHECK: ldp x29, x30, [sp, #16]
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; CHECK: ldp x28, x19, [sp], #32
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; CHECK-MACHO: sub sp, x29, #16
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; CHECK-MACHO: ldp x29, x30, [sp, #16]
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; CHECK-MACHO: ldp x20, x19, [sp], #32
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}
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declare i8* @llvm.stacksave()
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declare void @llvm.stackrestore(i8*)
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define void @test_scoped_alloca(i64 %n) {
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; CHECK-LABEL: test_scoped_alloca:
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%sp = call i8* @llvm.stacksave()
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; CHECK: mov [[SAVED_SP:x[0-9]+]], sp
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; CHECK: mov [[OLDSP:x[0-9]+]], sp
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%addr = alloca i8, i64 %n
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; CHECK: and [[SPDELTA:x[0-9]+]], {{x[0-9]+}}, #0xfffffffffffffff0
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; CHECK-DAG: sub [[NEWSP:x[0-9]+]], [[OLDSP]], [[SPDELTA]]
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; CHECK: mov sp, [[NEWSP]]
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call void @use_addr(i8* %addr)
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; CHECK: bl use_addr
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call void @llvm.stackrestore(i8* %sp)
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; CHECK: mov sp, [[SAVED_SP]]
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ret void
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}
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