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21c6e6f537
Mesa doesn't use this, and this is pattern matched already from fsub x, (ffloor x) llvm-svn: 258513
67 lines
3.4 KiB
LLVM
67 lines
3.4 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CI -check-prefix=FUNC %s
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declare double @llvm.fabs.f64(double) #0
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declare double @llvm.floor.f64(double) #0
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; FUNC-LABEL: {{^}}fract_f64:
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; GCN: v_fract_f64_e32 [[FRC:v\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]]
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; SI: v_mov_b32_e32 v[[UPLO:[0-9]+]], -1
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; SI: v_mov_b32_e32 v[[UPHI:[0-9]+]], 0x3fefffff
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; SI: v_min_f64 v{{\[}}[[MINLO:[0-9]+]]:[[MINHI:[0-9]+]]], v{{\[}}[[UPLO]]:[[UPHI]]], [[FRC]]
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; SI: v_cmp_class_f64_e64 [[COND:s\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO]]:[[HI]]], 3
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; SI: v_cndmask_b32_e64 v[[RESLO:[0-9]+]], v[[MINLO]], v[[LO]], [[COND]]
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; SI: v_cndmask_b32_e64 v[[RESHI:[0-9]+]], v[[MINHI]], v[[HI]], [[COND]]
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; SI: buffer_store_dwordx2 v{{\[}}[[RESLO]]:[[RESHI]]]
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; CI: buffer_store_dwordx2 [[FRC]]
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define void @fract_f64(double addrspace(1)* %out, double addrspace(1)* %src) #1 {
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%x = load double, double addrspace(1)* %src
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%floor.x = call double @llvm.floor.f64(double %x)
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%fract = fsub double %x, %floor.x
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store double %fract, double addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}fract_f64_neg:
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; GCN: v_fract_f64_e64 [[FRC:v\[[0-9]+:[0-9]+\]]], -v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]]
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; SI: v_mov_b32_e32 v[[UPLO:[0-9]+]], -1
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; SI: v_mov_b32_e32 v[[UPHI:[0-9]+]], 0x3fefffff
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; SI: v_min_f64 v{{\[}}[[MINLO:[0-9]+]]:[[MINHI:[0-9]+]]], v{{\[}}[[UPLO]]:[[UPHI]]], [[FRC]]
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; SI: v_cmp_class_f64_e64 [[COND:s\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO]]:[[HI]]], 3
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; SI: v_cndmask_b32_e64 v[[RESLO:[0-9]+]], v[[MINLO]], v[[LO]], [[COND]]
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; SI: v_cndmask_b32_e64 v[[RESHI:[0-9]+]], v[[MINHI]], v[[HI]], [[COND]]
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; SI: buffer_store_dwordx2 v{{\[}}[[RESLO]]:[[RESHI]]]
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; CI: buffer_store_dwordx2 [[FRC]]
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define void @fract_f64_neg(double addrspace(1)* %out, double addrspace(1)* %src) #1 {
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%x = load double, double addrspace(1)* %src
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%neg.x = fsub double -0.0, %x
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%floor.neg.x = call double @llvm.floor.f64(double %neg.x)
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%fract = fsub double %neg.x, %floor.neg.x
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store double %fract, double addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}fract_f64_neg_abs:
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; GCN: v_fract_f64_e64 [[FRC:v\[[0-9]+:[0-9]+\]]], -|v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]]|
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; SI: v_mov_b32_e32 v[[UPLO:[0-9]+]], -1
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; SI: v_mov_b32_e32 v[[UPHI:[0-9]+]], 0x3fefffff
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; SI: v_min_f64 v{{\[}}[[MINLO:[0-9]+]]:[[MINHI:[0-9]+]]], v{{\[}}[[UPLO]]:[[UPHI]]], [[FRC]]
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; SI: v_cmp_class_f64_e64 [[COND:s\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO]]:[[HI]]], 3
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; SI: v_cndmask_b32_e64 v[[RESLO:[0-9]+]], v[[MINLO]], v[[LO]], [[COND]]
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; SI: v_cndmask_b32_e64 v[[RESHI:[0-9]+]], v[[MINHI]], v[[HI]], [[COND]]
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; SI: buffer_store_dwordx2 v{{\[}}[[RESLO]]:[[RESHI]]]
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; CI: buffer_store_dwordx2 [[FRC]]
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define void @fract_f64_neg_abs(double addrspace(1)* %out, double addrspace(1)* %src) #1 {
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%x = load double, double addrspace(1)* %src
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%abs.x = call double @llvm.fabs.f64(double %x)
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%neg.abs.x = fsub double -0.0, %abs.x
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%floor.neg.abs.x = call double @llvm.floor.f64(double %neg.abs.x)
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%fract = fsub double %neg.abs.x, %floor.neg.abs.x
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store double %fract, double addrspace(1)* %out
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ret void
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}
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attributes #0 = { nounwind readnone }
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attributes #1 = { nounwind }
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