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cdae83c48c
Re-comitting with a change that avoids undefined uses getting put into the VRegUses list. The new algorithm remembers the uses encountered while walking backwards until a matching def is found. Contrary to the previous version this: - Works without LiveIntervals being available - Allows to increase the precision to subregisters/lanemasks (not used for now) The changes in the AMDGPU tests are necessary because the R600 scheduler is not stable with respect to the order of nodes in the ready queues. Differential Revision: http://reviews.llvm.org/D9068 llvm-svn: 254683
179 lines
6.5 KiB
LLVM
179 lines
6.5 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
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; FUNC-LABEL: {{^}}or_v2i32:
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; EG: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; EG: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; SI: v_or_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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; SI: v_or_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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define void @or_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
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%b_ptr = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %in, i32 1
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%a = load <2 x i32>, <2 x i32> addrspace(1) * %in
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%b = load <2 x i32>, <2 x i32> addrspace(1) * %b_ptr
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%result = or <2 x i32> %a, %b
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store <2 x i32> %result, <2 x i32> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}or_v4i32:
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; EG: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; EG: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; EG: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; EG: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; SI: v_or_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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; SI: v_or_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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; SI: v_or_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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; SI: v_or_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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define void @or_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
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%b_ptr = getelementptr <4 x i32>, <4 x i32> addrspace(1)* %in, i32 1
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%a = load <4 x i32>, <4 x i32> addrspace(1) * %in
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%b = load <4 x i32>, <4 x i32> addrspace(1) * %b_ptr
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%result = or <4 x i32> %a, %b
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store <4 x i32> %result, <4 x i32> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}scalar_or_i32:
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; SI: s_or_b32
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define void @scalar_or_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) {
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%or = or i32 %a, %b
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store i32 %or, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}vector_or_i32:
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; SI: v_or_b32_e32 v{{[0-9]}}
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define void @vector_or_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %a, i32 %b) {
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%loada = load i32, i32 addrspace(1)* %a
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%or = or i32 %loada, %b
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store i32 %or, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}scalar_or_literal_i32:
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; SI: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x1869f
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define void @scalar_or_literal_i32(i32 addrspace(1)* %out, i32 %a) {
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%or = or i32 %a, 99999
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store i32 %or, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}vector_or_literal_i32:
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; SI: v_or_b32_e32 v{{[0-9]+}}, 0xffff, v{{[0-9]+}}
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define void @vector_or_literal_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %a, i32 addrspace(1)* %b) {
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%loada = load i32, i32 addrspace(1)* %a, align 4
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%or = or i32 %loada, 65535
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store i32 %or, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}vector_or_inline_immediate_i32:
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; SI: v_or_b32_e32 v{{[0-9]+}}, 4, v{{[0-9]+}}
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define void @vector_or_inline_immediate_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %a, i32 addrspace(1)* %b) {
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%loada = load i32, i32 addrspace(1)* %a, align 4
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%or = or i32 %loada, 4
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store i32 %or, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}scalar_or_i64:
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; EG-DAG: OR_INT * T{{[0-9]\.[XYZW]}}, KC0[2].W, KC0[3].Y
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; EG-DAG: OR_INT * T{{[0-9]\.[XYZW]}}, KC0[3].X, KC0[3].Z
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; SI: s_or_b64
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define void @scalar_or_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) {
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%or = or i64 %a, %b
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store i64 %or, i64 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}vector_or_i64:
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; SI: v_or_b32_e32 v{{[0-9]}}
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; SI: v_or_b32_e32 v{{[0-9]}}
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define void @vector_or_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
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%loada = load i64, i64 addrspace(1)* %a, align 8
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%loadb = load i64, i64 addrspace(1)* %a, align 8
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%or = or i64 %loada, %loadb
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store i64 %or, i64 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}scalar_vector_or_i64:
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; SI: v_or_b32_e32 v{{[0-9]}}
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; SI: v_or_b32_e32 v{{[0-9]}}
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define void @scalar_vector_or_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 %b) {
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%loada = load i64, i64 addrspace(1)* %a
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%or = or i64 %loada, %b
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store i64 %or, i64 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}vector_or_i64_loadimm:
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; SI-DAG: s_mov_b32 [[LO_S_IMM:s[0-9]+]], 0xdf77987f
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; SI-DAG: s_movk_i32 [[HI_S_IMM:s[0-9]+]], 0x146f
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; SI-DAG: buffer_load_dwordx2 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}},
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; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[LO_S_IMM]], v[[LO_VREG]]
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; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[HI_S_IMM]], v[[HI_VREG]]
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; SI: s_endpgm
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define void @vector_or_i64_loadimm(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
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%loada = load i64, i64 addrspace(1)* %a, align 8
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%or = or i64 %loada, 22470723082367
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store i64 %or, i64 addrspace(1)* %out
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ret void
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}
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; FIXME: The or 0 should really be removed.
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; FUNC-LABEL: {{^}}vector_or_i64_imm:
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; SI: buffer_load_dwordx2 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}},
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; SI: v_or_b32_e32 {{v[0-9]+}}, 8, v[[LO_VREG]]
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; SI: v_or_b32_e32 {{v[0-9]+}}, 0, {{.*}}
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; SI: s_endpgm
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define void @vector_or_i64_imm(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
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%loada = load i64, i64 addrspace(1)* %a, align 8
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%or = or i64 %loada, 8
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store i64 %or, i64 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}trunc_i64_or_to_i32:
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; SI: s_load_dword s[[SREG0:[0-9]+]]
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; SI: s_load_dword s[[SREG1:[0-9]+]]
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; SI: s_or_b32 s[[SRESULT:[0-9]+]], s[[SREG1]], s[[SREG0]]
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; SI: v_mov_b32_e32 [[VRESULT:v[0-9]+]], s[[SRESULT]]
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; SI: buffer_store_dword [[VRESULT]],
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define void @trunc_i64_or_to_i32(i32 addrspace(1)* %out, i64 %a, i64 %b) {
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%add = or i64 %b, %a
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%trunc = trunc i64 %add to i32
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store i32 %trunc, i32 addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: {{^}}or_i1:
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; EG: OR_INT * {{\** *}}T{{[0-9]+\.[XYZW], PS, PV\.[XYZW]}}
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; SI: s_or_b64 s[{{[0-9]+:[0-9]+}}], vcc, s[{{[0-9]+:[0-9]+}}]
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define void @or_i1(i32 addrspace(1)* %out, float addrspace(1)* %in0, float addrspace(1)* %in1) {
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%a = load float, float addrspace(1)* %in0
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%b = load float, float addrspace(1)* %in1
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%acmp = fcmp oge float %a, 0.000000e+00
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%bcmp = fcmp oge float %b, 0.000000e+00
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%or = or i1 %acmp, %bcmp
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%result = zext i1 %or to i32
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store i32 %result, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}s_or_i1:
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; SI: s_or_b64 s[{{[0-9]+:[0-9]+}}], vcc, s[{{[0-9]+:[0-9]+}}]
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define void @s_or_i1(i1 addrspace(1)* %out, i32 %a, i32 %b, i32 %c, i32 %d) {
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%cmp0 = icmp eq i32 %a, %b
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%cmp1 = icmp eq i32 %c, %d
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%or = or i1 %cmp0, %cmp1
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store i1 %or, i1 addrspace(1)* %out
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ret void
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}
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