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One unusual feature of the z architecture is that the result of a previous load can be reused indefinitely for subsequent loads, even if a cache-coherent store to that location is performed by another CPU. A special serializing instruction must be used if you want to force a load to be reattempted. Since volatile loads are not supposed to be omitted in this way, we should insert a serializing instruction before each such load. The same goes for atomic loads. The patch implements this at the IR->DAG boundary, in a similar way to atomic fences. It is a no-op for targets other than SystemZ. llvm-svn: 196906
13 lines
276 B
LLVM
13 lines
276 B
LLVM
; Test 8-bit atomic stores.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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define void @f1(i8 %val, i8 *%src) {
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; CHECK-LABEL: f1:
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; CHECK: stc %r2, 0(%r3)
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; CHECK: bcr 1{{[45]}}, %r0
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; CHECK: br %r14
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store atomic i8 %val, i8 *%src seq_cst, align 1
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ret void
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}
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