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The ABI allows sub-128 vectors to be passed and returned in registers, with the vector occupying the upper part of a register. We therefore want to legalize those types by widening the vector rather than promoting the elements. The patch includes some simple tests for sub-128 vectors and also tests that we can recognize various pack sequences, some of which use sub-128 vectors as temporary results. One of these forms is based on the pack sequences generated by llvmpipe when no intrinsics are used. Signed unpacks are recognized as BUILD_VECTORs whose elements are individually sign-extended. Unsigned unpacks can have the equivalent form with zero extension, but they also occur as shuffles in which some elements are zero. Based on a patch by Richard Sandiford. llvm-svn: 236525
70 lines
1.9 KiB
LLVM
70 lines
1.9 KiB
LLVM
; Test insertions of register values into 0.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
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; Test v16i8 insertion into 0.
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define <16 x i8> @f1(i8 %val1, i8 %val2) {
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; CHECK-LABEL: f1:
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; CHECK: vgbm %v24, 0
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; CHECK-DAG: vlvgb %v24, %r2, 2
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; CHECK-DAG: vlvgb %v24, %r3, 12
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; CHECK: br %r14
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%vec1 = insertelement <16 x i8> zeroinitializer, i8 %val1, i32 2
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%vec2 = insertelement <16 x i8> %vec1, i8 %val2, i32 12
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ret <16 x i8> %vec2
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}
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; Test v8i16 insertion into 0.
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define <8 x i16> @f2(i16 %val1, i16 %val2) {
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; CHECK-LABEL: f2:
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; CHECK: vgbm %v24, 0
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; CHECK-DAG: vlvgh %v24, %r2, 3
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; CHECK-DAG: vlvgh %v24, %r3, 5
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; CHECK: br %r14
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%vec1 = insertelement <8 x i16> zeroinitializer, i16 %val1, i32 3
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%vec2 = insertelement <8 x i16> %vec1, i16 %val2, i32 5
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ret <8 x i16> %vec2
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}
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; Test v4i32 insertion into 0.
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define <4 x i32> @f3(i32 %val) {
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; CHECK-LABEL: f3:
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; CHECK: vgbm %v24, 0
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; CHECK: vlvgf %v24, %r2, 3
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; CHECK: br %r14
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%ret = insertelement <4 x i32> zeroinitializer, i32 %val, i32 3
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ret <4 x i32> %ret
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}
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; Test v2i64 insertion into 0.
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define <2 x i64> @f4(i64 %val) {
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; CHECK-LABEL: f4:
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; CHECK: lghi [[REG:%r[0-5]]], 0
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; CHECK: vlvgp %v24, [[REG]], %r2
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; CHECK: br %r14
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%ret = insertelement <2 x i64> zeroinitializer, i64 %val, i32 1
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ret <2 x i64> %ret
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}
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; Test v4f32 insertion into 0.
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define <4 x float> @f5(float %val) {
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; CHECK-LABEL: f5:
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; CHECK-DAG: vuplhf [[REG:%v[0-9]+]], %v0
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; CHECK-DAG: vgbm [[ZERO:%v[0-9]+]], 0
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; CHECK: vmrhg %v24, [[ZERO]], [[REG]]
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; CHECK: br %r14
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%ret = insertelement <4 x float> zeroinitializer, float %val, i32 3
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ret <4 x float> %ret
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}
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; Test v2f64 insertion into 0.
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define <2 x double> @f6(double %val) {
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; CHECK-LABEL: f6:
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; CHECK: vgbm [[REG:%v[0-9]+]], 0
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; CHECK: vmrhg %v24, [[REG]], %v0
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; CHECK: br %r14
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%ret = insertelement <2 x double> zeroinitializer, double %val, i32 1
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ret <2 x double> %ret
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}
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