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26eae94ea6
Those can occur when something between the sextload and the store is on the same chain and blocks isel. Fixes PR14887. llvm-svn: 172353
177 lines
4.5 KiB
LLVM
177 lines
4.5 KiB
LLVM
; RUN: llc < %s -march=x86-64 -mcpu=penryn | FileCheck -check-prefix=SSE41 %s
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; RUN: llc < %s -march=x86-64 -mcpu=corei7-avx | FileCheck -check-prefix=AVX1 %s
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; RUN: llc < %s -march=x86-64 -mcpu=core-avx2 | FileCheck -check-prefix=AVX2 %s
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; PR14887
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; These tests inject a store into the chain to test the inreg versions of pmovsx
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define void @test1(<2 x i8>* %in, <2 x i64>* %out) nounwind {
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%wide.load35 = load <2 x i8>* %in, align 1
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%sext = sext <2 x i8> %wide.load35 to <2 x i64>
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store <2 x i64> zeroinitializer, <2 x i64>* undef, align 8
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store <2 x i64> %sext, <2 x i64>* %out, align 8
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ret void
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; SSE41: test1:
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; SSE41: pmovsxbq
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; AVX1: test1:
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; AVX1: vpmovsxbq
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; AVX2: test1:
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; AVX2: vpmovsxbq
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}
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define void @test2(<4 x i8>* %in, <4 x i64>* %out) nounwind {
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%wide.load35 = load <4 x i8>* %in, align 1
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%sext = sext <4 x i8> %wide.load35 to <4 x i64>
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store <4 x i64> zeroinitializer, <4 x i64>* undef, align 8
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store <4 x i64> %sext, <4 x i64>* %out, align 8
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ret void
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; AVX2: test2:
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; AVX2: vpmovsxbq
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}
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define void @test3(<4 x i8>* %in, <4 x i32>* %out) nounwind {
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%wide.load35 = load <4 x i8>* %in, align 1
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%sext = sext <4 x i8> %wide.load35 to <4 x i32>
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store <4 x i32> zeroinitializer, <4 x i32>* undef, align 8
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store <4 x i32> %sext, <4 x i32>* %out, align 8
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ret void
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; SSE41: test3:
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; SSE41: pmovsxbd
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; AVX1: test3:
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; AVX1: vpmovsxbd
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; AVX2: test3:
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; AVX2: vpmovsxbd
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}
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define void @test4(<8 x i8>* %in, <8 x i32>* %out) nounwind {
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%wide.load35 = load <8 x i8>* %in, align 1
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%sext = sext <8 x i8> %wide.load35 to <8 x i32>
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store <8 x i32> zeroinitializer, <8 x i32>* undef, align 8
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store <8 x i32> %sext, <8 x i32>* %out, align 8
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ret void
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; AVX2: test4:
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; AVX2: vpmovsxbd
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}
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define void @test5(<8 x i8>* %in, <8 x i16>* %out) nounwind {
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%wide.load35 = load <8 x i8>* %in, align 1
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%sext = sext <8 x i8> %wide.load35 to <8 x i16>
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store <8 x i16> zeroinitializer, <8 x i16>* undef, align 8
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store <8 x i16> %sext, <8 x i16>* %out, align 8
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ret void
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; SSE41: test5:
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; SSE41: pmovsxbw
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; AVX1: test5:
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; AVX1: vpmovsxbw
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; AVX2: test5:
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; AVX2: vpmovsxbw
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}
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define void @test6(<16 x i8>* %in, <16 x i16>* %out) nounwind {
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%wide.load35 = load <16 x i8>* %in, align 1
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%sext = sext <16 x i8> %wide.load35 to <16 x i16>
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store <16 x i16> zeroinitializer, <16 x i16>* undef, align 8
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store <16 x i16> %sext, <16 x i16>* %out, align 8
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ret void
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; AVX2: test6:
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; FIXME: v16i8 -> v16i16 is scalarized.
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; AVX2-NOT: pmovsx
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}
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define void @test7(<2 x i16>* %in, <2 x i64>* %out) nounwind {
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%wide.load35 = load <2 x i16>* %in, align 1
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%sext = sext <2 x i16> %wide.load35 to <2 x i64>
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store <2 x i64> zeroinitializer, <2 x i64>* undef, align 8
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store <2 x i64> %sext, <2 x i64>* %out, align 8
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ret void
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; SSE41: test7:
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; SSE41: pmovsxwq
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; AVX1: test7:
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; AVX1: vpmovsxwq
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; AVX2: test7:
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; AVX2: vpmovsxwq
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}
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define void @test8(<4 x i16>* %in, <4 x i64>* %out) nounwind {
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%wide.load35 = load <4 x i16>* %in, align 1
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%sext = sext <4 x i16> %wide.load35 to <4 x i64>
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store <4 x i64> zeroinitializer, <4 x i64>* undef, align 8
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store <4 x i64> %sext, <4 x i64>* %out, align 8
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ret void
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; AVX2: test8:
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; AVX2: vpmovsxwq
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}
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define void @test9(<4 x i16>* %in, <4 x i32>* %out) nounwind {
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%wide.load35 = load <4 x i16>* %in, align 1
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%sext = sext <4 x i16> %wide.load35 to <4 x i32>
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store <4 x i32> zeroinitializer, <4 x i32>* undef, align 8
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store <4 x i32> %sext, <4 x i32>* %out, align 8
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ret void
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; SSE41: test9:
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; SSE41: pmovsxwd
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; AVX1: test9:
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; AVX1: vpmovsxwd
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; AVX2: test9:
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; AVX2: vpmovsxwd
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}
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define void @test10(<8 x i16>* %in, <8 x i32>* %out) nounwind {
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%wide.load35 = load <8 x i16>* %in, align 1
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%sext = sext <8 x i16> %wide.load35 to <8 x i32>
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store <8 x i32> zeroinitializer, <8 x i32>* undef, align 8
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store <8 x i32> %sext, <8 x i32>* %out, align 8
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ret void
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; AVX2: test10:
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; AVX2: vpmovsxwd
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}
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define void @test11(<2 x i32>* %in, <2 x i64>* %out) nounwind {
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%wide.load35 = load <2 x i32>* %in, align 1
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%sext = sext <2 x i32> %wide.load35 to <2 x i64>
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store <2 x i64> zeroinitializer, <2 x i64>* undef, align 8
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store <2 x i64> %sext, <2 x i64>* %out, align 8
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ret void
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; SSE41: test11:
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; SSE41: pmovsxdq
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; AVX1: test11:
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; AVX1: vpmovsxdq
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; AVX2: test11:
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; AVX2: vpmovsxdq
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}
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define void @test12(<4 x i32>* %in, <4 x i64>* %out) nounwind {
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%wide.load35 = load <4 x i32>* %in, align 1
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%sext = sext <4 x i32> %wide.load35 to <4 x i64>
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store <4 x i64> zeroinitializer, <4 x i64>* undef, align 8
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store <4 x i64> %sext, <4 x i64>* %out, align 8
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ret void
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; AVX2: test12:
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; AVX2: vpmovsxdq
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}
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