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877 lines
36 KiB
TableGen
877 lines
36 KiB
TableGen
//===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Mips implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Instruction format superclass
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//===----------------------------------------------------------------------===//
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include "MipsInstrFormats.td"
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//===----------------------------------------------------------------------===//
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// Mips profiles and nodes
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//===----------------------------------------------------------------------===//
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def SDT_MipsRet : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
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def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
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def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
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SDTCisSameAs<1, 2>,
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SDTCisSameAs<3, 4>,
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SDTCisInt<4>]>;
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def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
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def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
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def SDT_MipsMAddMSub : SDTypeProfile<0, 4,
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[SDTCisVT<0, i32>, SDTCisSameAs<0, 1>,
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SDTCisSameAs<1, 2>,
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SDTCisSameAs<2, 3>]>;
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def SDT_MipsDivRem : SDTypeProfile<0, 2,
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[SDTCisVT<0, i32>,
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SDTCisSameAs<0, 1>]>;
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def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
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def SDT_MipsDynAlloc : SDTypeProfile<1, 1, [SDTCisVT<0, i32>,
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SDTCisVT<1, iPTR>]>;
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// Call
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def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
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[SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
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SDNPVariadic]>;
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// Hi and Lo nodes are used to handle global addresses. Used on
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// MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
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// static model. (nothing to do with Mips Registers Hi and Lo)
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def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
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def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
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def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
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// TlsGd node is used to handle General Dynamic TLS
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def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
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// TprelHi and TprelLo nodes are used to handle Local Exec TLS
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def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
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def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
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// Thread pointer
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def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
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// Return
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def MipsRet : SDNode<"MipsISD::Ret", SDT_MipsRet, [SDNPHasChain,
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SDNPOptInGlue]>;
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// These are target-independent nodes, but have target-specific formats.
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def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
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[SDNPHasChain, SDNPOutGlue]>;
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def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
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[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
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// MAdd*/MSub* nodes
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def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub,
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[SDNPOptInGlue, SDNPOutGlue]>;
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def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub,
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[SDNPOptInGlue, SDNPOutGlue]>;
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def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub,
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[SDNPOptInGlue, SDNPOutGlue]>;
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def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub,
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[SDNPOptInGlue, SDNPOutGlue]>;
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// DivRem(u) nodes
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def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsDivRem,
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[SDNPOutGlue]>;
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def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsDivRem,
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[SDNPOutGlue]>;
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// Target constant nodes that are not part of any isel patterns and remain
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// unchanged can cause instructions with illegal operands to be emitted.
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// Wrapper node patterns give the instruction selector a chance to replace
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// target constant nodes that would otherwise remain unchanged with ADDiu
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// nodes. Without these wrapper node patterns, the following conditional move
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// instrucion is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
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// compiled:
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// movn %got(d)($gp), %got(c)($gp), $4
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// This instruction is illegal since movn can take only register operands.
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def MipsWrapperPIC : SDNode<"MipsISD::WrapperPIC", SDTIntUnaryOp>;
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// Pointer to dynamically allocated stack area.
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def MipsDynAlloc : SDNode<"MipsISD::DynAlloc", SDT_MipsDynAlloc,
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[SDNPHasChain, SDNPInGlue]>;
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//===----------------------------------------------------------------------===//
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// Mips Instruction Predicate Definitions.
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//===----------------------------------------------------------------------===//
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def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">;
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def HasBitCount : Predicate<"Subtarget.hasBitCount()">;
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def HasSwap : Predicate<"Subtarget.hasSwap()">;
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def HasCondMov : Predicate<"Subtarget.hasCondMov()">;
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def IsMips32 : Predicate<"Subtarget.isMips32()">;
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def IsMips32r2 : Predicate<"Subtarget.isMips32r2()">;
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//===----------------------------------------------------------------------===//
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// Mips Operand, Complex Patterns and Transformations Definitions.
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//===----------------------------------------------------------------------===//
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// Instruction operand types
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def brtarget : Operand<OtherVT>;
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def calltarget : Operand<i32>;
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def simm16 : Operand<i32>;
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def shamt : Operand<i32>;
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// Unsigned Operand
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def uimm16 : Operand<i32> {
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let PrintMethod = "printUnsignedImm";
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}
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// Address operand
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def mem : Operand<i32> {
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let PrintMethod = "printMemOperand";
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let MIOperandInfo = (ops simm16, CPURegs);
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}
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// Transformation Function - get the lower 16 bits.
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def LO16 : SDNodeXForm<imm, [{
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return getI32Imm((unsigned)N->getZExtValue() & 0xFFFF);
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}]>;
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// Transformation Function - get the higher 16 bits.
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def HI16 : SDNodeXForm<imm, [{
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return getI32Imm((unsigned)N->getZExtValue() >> 16);
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}]>;
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// Node immediate fits as 16-bit sign extended on target immediate.
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// e.g. addi, andi
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def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
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// Node immediate fits as 16-bit zero extended on target immediate.
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// The LO16 param means that only the lower 16 bits of the node
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// immediate are caught.
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// e.g. addiu, sltiu
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def immZExt16 : PatLeaf<(imm), [{
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if (N->getValueType(0) == MVT::i32)
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return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
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else
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return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
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}], LO16>;
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// shamt field must fit in 5 bits.
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def immZExt5 : PatLeaf<(imm), [{
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return N->getZExtValue() == ((N->getZExtValue()) & 0x1f) ;
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}]>;
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// Mips Address Mode! SDNode frameindex could possibily be a match
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// since load and store instructions from stack used it.
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def addr : ComplexPattern<iPTR, 2, "SelectAddr", [frameindex], []>;
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//===----------------------------------------------------------------------===//
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// Instructions specific format
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//===----------------------------------------------------------------------===//
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// Arithmetic 3 register operands
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class ArithR<bits<6> op, bits<6> func, string instr_asm, SDNode OpNode,
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InstrItinClass itin, bit isComm = 0>:
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FR<op, func, (outs CPURegs:$dst), (ins CPURegs:$b, CPURegs:$c),
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!strconcat(instr_asm, "\t$dst, $b, $c"),
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[(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], itin> {
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let isCommutable = isComm;
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}
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class ArithOverflowR<bits<6> op, bits<6> func, string instr_asm,
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bit isComm = 0>:
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FR<op, func, (outs CPURegs:$dst), (ins CPURegs:$b, CPURegs:$c),
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!strconcat(instr_asm, "\t$dst, $b, $c"), [], IIAlu> {
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let isCommutable = isComm;
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}
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// Arithmetic 2 register operands
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class ArithI<bits<6> op, string instr_asm, SDNode OpNode,
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Operand Od, PatLeaf imm_type> :
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FI<op, (outs CPURegs:$dst), (ins CPURegs:$b, Od:$c),
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!strconcat(instr_asm, "\t$dst, $b, $c"),
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[(set CPURegs:$dst, (OpNode CPURegs:$b, imm_type:$c))], IIAlu>;
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class ArithOverflowI<bits<6> op, string instr_asm, SDNode OpNode,
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Operand Od, PatLeaf imm_type> :
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FI<op, (outs CPURegs:$dst), (ins CPURegs:$b, Od:$c),
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!strconcat(instr_asm, "\t$dst, $b, $c"), [], IIAlu>;
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// Arithmetic Multiply ADD/SUB
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let rd = 0, shamt = 0, Defs = [HI, LO], Uses = [HI, LO] in
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class MArithR<bits<6> func, string instr_asm, SDNode op, bit isComm = 0> :
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FR<0x1c, func, (outs), (ins CPURegs:$rs, CPURegs:$rt),
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!strconcat(instr_asm, "\t$rs, $rt"),
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[(op CPURegs:$rs, CPURegs:$rt, LO, HI)], IIImul> {
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let isCommutable = isComm;
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}
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// Logical
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let isCommutable = 1 in
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class LogicR<bits<6> func, string instr_asm, SDNode OpNode>:
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FR<0x00, func, (outs CPURegs:$dst), (ins CPURegs:$b, CPURegs:$c),
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!strconcat(instr_asm, "\t$dst, $b, $c"),
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[(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], IIAlu>;
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class LogicI<bits<6> op, string instr_asm, SDNode OpNode>:
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FI<op, (outs CPURegs:$dst), (ins CPURegs:$b, uimm16:$c),
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!strconcat(instr_asm, "\t$dst, $b, $c"),
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[(set CPURegs:$dst, (OpNode CPURegs:$b, immZExt16:$c))], IIAlu>;
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let isCommutable = 1 in
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class LogicNOR<bits<6> op, bits<6> func, string instr_asm>:
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FR<op, func, (outs CPURegs:$dst), (ins CPURegs:$b, CPURegs:$c),
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!strconcat(instr_asm, "\t$dst, $b, $c"),
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[(set CPURegs:$dst, (not (or CPURegs:$b, CPURegs:$c)))], IIAlu>;
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// Shifts
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class LogicR_shift_rotate_imm<bits<6> func, bits<5> _rs, string instr_asm,
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SDNode OpNode>:
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FR<0x00, func, (outs CPURegs:$dst), (ins CPURegs:$b, shamt:$c),
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!strconcat(instr_asm, "\t$dst, $b, $c"),
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[(set CPURegs:$dst, (OpNode CPURegs:$b, immZExt5:$c))], IIAlu> {
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let rs = _rs;
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}
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class LogicR_shift_rotate_reg<bits<6> func, bits<5> _shamt, string instr_asm,
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SDNode OpNode>:
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FR<0x00, func, (outs CPURegs:$dst), (ins CPURegs:$c, CPURegs:$b),
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!strconcat(instr_asm, "\t$dst, $b, $c"),
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[(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], IIAlu> {
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let shamt = _shamt;
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}
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// Load Upper Imediate
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class LoadUpper<bits<6> op, string instr_asm>:
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FI< op,
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(outs CPURegs:$dst),
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(ins uimm16:$imm),
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!strconcat(instr_asm, "\t$dst, $imm"),
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[], IIAlu>;
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// Memory Load/Store
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let canFoldAsLoad = 1, hasDelaySlot = 1 in
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class LoadM<bits<6> op, string instr_asm, PatFrag OpNode>:
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FI<op, (outs CPURegs:$dst), (ins mem:$addr),
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!strconcat(instr_asm, "\t$dst, $addr"),
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[(set CPURegs:$dst, (OpNode addr:$addr))], IILoad>;
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class StoreM<bits<6> op, string instr_asm, PatFrag OpNode>:
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FI<op, (outs), (ins CPURegs:$dst, mem:$addr),
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!strconcat(instr_asm, "\t$dst, $addr"),
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[(OpNode CPURegs:$dst, addr:$addr)], IIStore>;
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// Conditional Branch
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let isBranch = 1, isTerminator=1, hasDelaySlot = 1 in {
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class CBranch<bits<6> op, string instr_asm, PatFrag cond_op>:
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FI<op, (outs), (ins CPURegs:$a, CPURegs:$b, brtarget:$offset),
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!strconcat(instr_asm, "\t$a, $b, $offset"),
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[(brcond (cond_op CPURegs:$a, CPURegs:$b), bb:$offset)],
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IIBranch>;
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class CBranchZero<bits<6> op, string instr_asm, PatFrag cond_op>:
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FI<op, (outs), (ins CPURegs:$src, brtarget:$offset),
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!strconcat(instr_asm, "\t$src, $offset"),
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[(brcond (cond_op CPURegs:$src, 0), bb:$offset)],
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IIBranch>;
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}
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// SetCC
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class SetCC_R<bits<6> op, bits<6> func, string instr_asm,
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PatFrag cond_op>:
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FR<op, func, (outs CPURegs:$dst), (ins CPURegs:$b, CPURegs:$c),
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!strconcat(instr_asm, "\t$dst, $b, $c"),
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[(set CPURegs:$dst, (cond_op CPURegs:$b, CPURegs:$c))],
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IIAlu>;
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class SetCC_I<bits<6> op, string instr_asm, PatFrag cond_op,
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Operand Od, PatLeaf imm_type>:
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FI<op, (outs CPURegs:$dst), (ins CPURegs:$b, Od:$c),
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!strconcat(instr_asm, "\t$dst, $b, $c"),
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[(set CPURegs:$dst, (cond_op CPURegs:$b, imm_type:$c))],
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IIAlu>;
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// Unconditional branch
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let isBranch=1, isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
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class JumpFJ<bits<6> op, string instr_asm>:
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FJ<op, (outs), (ins brtarget:$target),
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!strconcat(instr_asm, "\t$target"), [(br bb:$target)], IIBranch>;
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let isBranch=1, isTerminator=1, isBarrier=1, rd=0, hasDelaySlot = 1 in
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class JumpFR<bits<6> op, bits<6> func, string instr_asm>:
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FR<op, func, (outs), (ins CPURegs:$target),
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!strconcat(instr_asm, "\t$target"), [(brind CPURegs:$target)], IIBranch>;
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// Jump and Link (Call)
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let isCall=1, hasDelaySlot=1,
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// All calls clobber the non-callee saved registers...
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Defs = [AT, V0, V1, A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, T6, T7, T8, T9,
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K0, K1, D0, D1, D2, D3, D4, D5, D6, D7, D8, D9], Uses = [GP] in {
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class JumpLink<bits<6> op, string instr_asm>:
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FJ<op, (outs), (ins calltarget:$target, variable_ops),
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!strconcat(instr_asm, "\t$target"), [(MipsJmpLink imm:$target)],
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IIBranch>;
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let rd=31 in
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class JumpLinkReg<bits<6> op, bits<6> func, string instr_asm>:
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FR<op, func, (outs), (ins CPURegs:$rs, variable_ops),
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!strconcat(instr_asm, "\t$rs"), [(MipsJmpLink CPURegs:$rs)], IIBranch>;
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class BranchLink<string instr_asm>:
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FI<0x1, (outs), (ins CPURegs:$rs, brtarget:$target, variable_ops),
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!strconcat(instr_asm, "\t$rs, $target"), [], IIBranch>;
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}
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// Mul, Div
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let Defs = [HI, LO] in {
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let isCommutable = 1 in
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class Mul<bits<6> func, string instr_asm, InstrItinClass itin>:
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FR<0x00, func, (outs), (ins CPURegs:$a, CPURegs:$b),
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!strconcat(instr_asm, "\t$a, $b"), [], itin>;
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class Div<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>:
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FR<0x00, func, (outs), (ins CPURegs:$a, CPURegs:$b),
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!strconcat(instr_asm, "\t$$zero, $a, $b"),
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[(op CPURegs:$a, CPURegs:$b)], itin>;
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}
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// Move from Hi/Lo
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class MoveFromLOHI<bits<6> func, string instr_asm>:
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FR<0x00, func, (outs CPURegs:$dst), (ins),
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!strconcat(instr_asm, "\t$dst"), [], IIHiLo>;
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class MoveToLOHI<bits<6> func, string instr_asm>:
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FR<0x00, func, (outs), (ins CPURegs:$src),
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!strconcat(instr_asm, "\t$src"), [], IIHiLo>;
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class EffectiveAddress<string instr_asm> :
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FI<0x09, (outs CPURegs:$dst), (ins mem:$addr),
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instr_asm, [(set CPURegs:$dst, addr:$addr)], IIAlu>;
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// Count Leading Ones/Zeros in Word
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class CountLeading<bits<6> func, string instr_asm, list<dag> pattern>:
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FR<0x1c, func, (outs CPURegs:$dst), (ins CPURegs:$src),
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!strconcat(instr_asm, "\t$dst, $src"), pattern, IIAlu>,
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Requires<[HasBitCount]> {
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let shamt = 0;
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let rt = rd;
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}
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// Sign Extend in Register.
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class SignExtInReg<bits<6> func, string instr_asm, ValueType vt>:
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FR<0x3f, func, (outs CPURegs:$dst), (ins CPURegs:$src),
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!strconcat(instr_asm, "\t$dst, $src"),
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[(set CPURegs:$dst, (sext_inreg CPURegs:$src, vt))], NoItinerary>;
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// Byte Swap
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class ByteSwap<bits<6> func, string instr_asm>:
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FR<0x1f, func, (outs CPURegs:$dst), (ins CPURegs:$src),
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!strconcat(instr_asm, "\t$dst, $src"),
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[(set CPURegs:$dst, (bswap CPURegs:$src))], NoItinerary>;
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// Conditional Move
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class CondMov<bits<6> func, string instr_asm, PatLeaf MovCode>:
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FR<0x00, func, (outs CPURegs:$dst), (ins CPURegs:$F, CPURegs:$T,
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CPURegs:$cond), !strconcat(instr_asm, "\t$dst, $T, $cond"),
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[], NoItinerary>;
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// Read Hardware
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class ReadHardware: FR<0x1f, 0x3b, (outs CPURegs:$dst), (ins HWRegs:$src),
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|
"rdhwr\t$dst, $src", [], IIAlu> {
|
|
let rs = 0;
|
|
let shamt = 0;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Pseudo instructions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// As stack alignment is always done with addiu, we need a 16-bit immediate
|
|
let Defs = [SP], Uses = [SP] in {
|
|
def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins uimm16:$amt),
|
|
"!ADJCALLSTACKDOWN $amt",
|
|
[(callseq_start timm:$amt)]>;
|
|
def ADJCALLSTACKUP : MipsPseudo<(outs), (ins uimm16:$amt1, uimm16:$amt2),
|
|
"!ADJCALLSTACKUP $amt1",
|
|
[(callseq_end timm:$amt1, timm:$amt2)]>;
|
|
}
|
|
|
|
// Some assembly macros need to avoid pseudoinstructions and assembler
|
|
// automatic reodering, we should reorder ourselves.
|
|
def MACRO : MipsPseudo<(outs), (ins), ".set\tmacro", []>;
|
|
def REORDER : MipsPseudo<(outs), (ins), ".set\treorder", []>;
|
|
def NOMACRO : MipsPseudo<(outs), (ins), ".set\tnomacro", []>;
|
|
def NOREORDER : MipsPseudo<(outs), (ins), ".set\tnoreorder", []>;
|
|
|
|
// These macros are inserted to prevent GAS from complaining
|
|
// when using the AT register.
|
|
def NOAT : MipsPseudo<(outs), (ins), ".set\tnoat", []>;
|
|
def ATMACRO : MipsPseudo<(outs), (ins), ".set\tat", []>;
|
|
|
|
// When handling PIC code the assembler needs .cpload and .cprestore
|
|
// directives. If the real instructions corresponding these directives
|
|
// are used, we have the same behavior, but get also a bunch of warnings
|
|
// from the assembler.
|
|
def CPLOAD : MipsPseudo<(outs), (ins CPURegs:$picreg), ".cpload\t$picreg", []>;
|
|
def CPRESTORE : MipsPseudo<(outs), (ins i32imm:$loc), ".cprestore\t$loc\n", []>;
|
|
|
|
let usesCustomInserter = 1 in {
|
|
def ATOMIC_LOAD_ADD_I8 : MipsPseudo<
|
|
(outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr),
|
|
"atomic_load_add_8\t$dst, $ptr, $incr",
|
|
[(set CPURegs:$dst, (atomic_load_add_8 CPURegs:$ptr, CPURegs:$incr))]>;
|
|
def ATOMIC_LOAD_ADD_I16 : MipsPseudo<
|
|
(outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr),
|
|
"atomic_load_add_16\t$dst, $ptr, $incr",
|
|
[(set CPURegs:$dst, (atomic_load_add_16 CPURegs:$ptr, CPURegs:$incr))]>;
|
|
def ATOMIC_LOAD_ADD_I32 : MipsPseudo<
|
|
(outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr),
|
|
"atomic_load_add_32\t$dst, $ptr, $incr",
|
|
[(set CPURegs:$dst, (atomic_load_add_32 CPURegs:$ptr, CPURegs:$incr))]>;
|
|
|
|
def ATOMIC_LOAD_SUB_I8 : MipsPseudo<
|
|
(outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr),
|
|
"atomic_load_sub_8\t$dst, $ptr, $incr",
|
|
[(set CPURegs:$dst, (atomic_load_sub_8 CPURegs:$ptr, CPURegs:$incr))]>;
|
|
def ATOMIC_LOAD_SUB_I16 : MipsPseudo<
|
|
(outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr),
|
|
"atomic_load_sub_16\t$dst, $ptr, $incr",
|
|
[(set CPURegs:$dst, (atomic_load_sub_16 CPURegs:$ptr, CPURegs:$incr))]>;
|
|
def ATOMIC_LOAD_SUB_I32 : MipsPseudo<
|
|
(outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr),
|
|
"atomic_load_sub_32\t$dst, $ptr, $incr",
|
|
[(set CPURegs:$dst, (atomic_load_sub_32 CPURegs:$ptr, CPURegs:$incr))]>;
|
|
|
|
def ATOMIC_LOAD_AND_I8 : MipsPseudo<
|
|
(outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr),
|
|
"atomic_load_and_8\t$dst, $ptr, $incr",
|
|
[(set CPURegs:$dst, (atomic_load_and_8 CPURegs:$ptr, CPURegs:$incr))]>;
|
|
def ATOMIC_LOAD_AND_I16 : MipsPseudo<
|
|
(outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr),
|
|
"atomic_load_and_16\t$dst, $ptr, $incr",
|
|
[(set CPURegs:$dst, (atomic_load_and_16 CPURegs:$ptr, CPURegs:$incr))]>;
|
|
def ATOMIC_LOAD_AND_I32 : MipsPseudo<
|
|
(outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr),
|
|
"atomic_load_and_32\t$dst, $ptr, $incr",
|
|
[(set CPURegs:$dst, (atomic_load_and_32 CPURegs:$ptr, CPURegs:$incr))]>;
|
|
|
|
def ATOMIC_LOAD_OR_I8 : MipsPseudo<
|
|
(outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr),
|
|
"atomic_load_or_8\t$dst, $ptr, $incr",
|
|
[(set CPURegs:$dst, (atomic_load_or_8 CPURegs:$ptr, CPURegs:$incr))]>;
|
|
def ATOMIC_LOAD_OR_I16 : MipsPseudo<
|
|
(outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr),
|
|
"atomic_load_or_16\t$dst, $ptr, $incr",
|
|
[(set CPURegs:$dst, (atomic_load_or_16 CPURegs:$ptr, CPURegs:$incr))]>;
|
|
def ATOMIC_LOAD_OR_I32 : MipsPseudo<
|
|
(outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr),
|
|
"atomic_load_or_32\t$dst, $ptr, $incr",
|
|
[(set CPURegs:$dst, (atomic_load_or_32 CPURegs:$ptr, CPURegs:$incr))]>;
|
|
|
|
def ATOMIC_LOAD_XOR_I8 : MipsPseudo<
|
|
(outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr),
|
|
"atomic_load_xor_8\t$dst, $ptr, $incr",
|
|
[(set CPURegs:$dst, (atomic_load_xor_8 CPURegs:$ptr, CPURegs:$incr))]>;
|
|
def ATOMIC_LOAD_XOR_I16 : MipsPseudo<
|
|
(outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr),
|
|
"atomic_load_xor_16\t$dst, $ptr, $incr",
|
|
[(set CPURegs:$dst, (atomic_load_xor_16 CPURegs:$ptr, CPURegs:$incr))]>;
|
|
def ATOMIC_LOAD_XOR_I32 : MipsPseudo<
|
|
(outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr),
|
|
"atomic_load_xor_32\t$dst, $ptr, $incr",
|
|
[(set CPURegs:$dst, (atomic_load_xor_32 CPURegs:$ptr, CPURegs:$incr))]>;
|
|
|
|
def ATOMIC_LOAD_NAND_I8 : MipsPseudo<
|
|
(outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr),
|
|
"atomic_load_nand_8\t$dst, $ptr, $incr",
|
|
[(set CPURegs:$dst, (atomic_load_nand_8 CPURegs:$ptr, CPURegs:$incr))]>;
|
|
def ATOMIC_LOAD_NAND_I16 : MipsPseudo<
|
|
(outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr),
|
|
"atomic_load_nand_16\t$dst, $ptr, $incr",
|
|
[(set CPURegs:$dst, (atomic_load_nand_16 CPURegs:$ptr, CPURegs:$incr))]>;
|
|
def ATOMIC_LOAD_NAND_I32 : MipsPseudo<
|
|
(outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr),
|
|
"atomic_load_nand_32\t$dst, $ptr, $incr",
|
|
[(set CPURegs:$dst, (atomic_load_nand_32 CPURegs:$ptr, CPURegs:$incr))]>;
|
|
|
|
def ATOMIC_SWAP_I8 : MipsPseudo<
|
|
(outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$val),
|
|
"atomic_swap_8\t$dst, $ptr, $val",
|
|
[(set CPURegs:$dst, (atomic_swap_8 CPURegs:$ptr, CPURegs:$val))]>;
|
|
def ATOMIC_SWAP_I16 : MipsPseudo<
|
|
(outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$val),
|
|
"atomic_swap_16\t$dst, $ptr, $val",
|
|
[(set CPURegs:$dst, (atomic_swap_16 CPURegs:$ptr, CPURegs:$val))]>;
|
|
def ATOMIC_SWAP_I32 : MipsPseudo<
|
|
(outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$val),
|
|
"atomic_swap_32\t$dst, $ptr, $val",
|
|
[(set CPURegs:$dst, (atomic_swap_32 CPURegs:$ptr, CPURegs:$val))]>;
|
|
|
|
def ATOMIC_CMP_SWAP_I8 : MipsPseudo<
|
|
(outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$oldval, CPURegs:$newval),
|
|
"atomic_cmp_swap_8\t$dst, $ptr, $oldval, $newval",
|
|
[(set CPURegs:$dst,
|
|
(atomic_cmp_swap_8 CPURegs:$ptr, CPURegs:$oldval, CPURegs:$newval))]>;
|
|
def ATOMIC_CMP_SWAP_I16 : MipsPseudo<
|
|
(outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$oldval, CPURegs:$newval),
|
|
"atomic_cmp_swap_16\t$dst, $ptr, $oldval, $newval",
|
|
[(set CPURegs:$dst,
|
|
(atomic_cmp_swap_16 CPURegs:$ptr, CPURegs:$oldval, CPURegs:$newval))]>;
|
|
def ATOMIC_CMP_SWAP_I32 : MipsPseudo<
|
|
(outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$oldval, CPURegs:$newval),
|
|
"atomic_cmp_swap_32\t$dst, $ptr, $oldval, $newval",
|
|
[(set CPURegs:$dst,
|
|
(atomic_cmp_swap_32 CPURegs:$ptr, CPURegs:$oldval, CPURegs:$newval))]>;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Instruction definition
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// MipsI Instructions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
/// Arithmetic Instructions (ALU Immediate)
|
|
def ADDiu : ArithI<0x09, "addiu", add, simm16, immSExt16>;
|
|
def ADDi : ArithOverflowI<0x08, "addi", add, simm16, immSExt16>;
|
|
def SLTi : SetCC_I<0x0a, "slti", setlt, simm16, immSExt16>;
|
|
def SLTiu : SetCC_I<0x0b, "sltiu", setult, simm16, immSExt16>;
|
|
def ANDi : LogicI<0x0c, "andi", and>;
|
|
def ORi : LogicI<0x0d, "ori", or>;
|
|
def XORi : LogicI<0x0e, "xori", xor>;
|
|
def LUi : LoadUpper<0x0f, "lui">;
|
|
|
|
/// Arithmetic Instructions (3-Operand, R-Type)
|
|
def ADDu : ArithR<0x00, 0x21, "addu", add, IIAlu, 1>;
|
|
def SUBu : ArithR<0x00, 0x23, "subu", sub, IIAlu>;
|
|
def ADD : ArithOverflowR<0x00, 0x20, "add", 1>;
|
|
def SUB : ArithOverflowR<0x00, 0x22, "sub">;
|
|
def SLT : SetCC_R<0x00, 0x2a, "slt", setlt>;
|
|
def SLTu : SetCC_R<0x00, 0x2b, "sltu", setult>;
|
|
def AND : LogicR<0x24, "and", and>;
|
|
def OR : LogicR<0x25, "or", or>;
|
|
def XOR : LogicR<0x26, "xor", xor>;
|
|
def NOR : LogicNOR<0x00, 0x27, "nor">;
|
|
|
|
/// Shift Instructions
|
|
def SLL : LogicR_shift_rotate_imm<0x00, 0x00, "sll", shl>;
|
|
def SRL : LogicR_shift_rotate_imm<0x02, 0x00, "srl", srl>;
|
|
def SRA : LogicR_shift_rotate_imm<0x03, 0x00, "sra", sra>;
|
|
def SLLV : LogicR_shift_rotate_reg<0x04, 0x00, "sllv", shl>;
|
|
def SRLV : LogicR_shift_rotate_reg<0x06, 0x00, "srlv", srl>;
|
|
def SRAV : LogicR_shift_rotate_reg<0x07, 0x00, "srav", sra>;
|
|
|
|
// Rotate Instructions
|
|
let Predicates = [IsMips32r2] in {
|
|
def ROTR : LogicR_shift_rotate_imm<0x02, 0x01, "rotr", rotr>;
|
|
def ROTRV : LogicR_shift_rotate_reg<0x06, 0x01, "rotrv", rotr>;
|
|
}
|
|
|
|
/// Load and Store Instructions
|
|
def LB : LoadM<0x20, "lb", sextloadi8>;
|
|
def LBu : LoadM<0x24, "lbu", zextloadi8>;
|
|
def LH : LoadM<0x21, "lh", sextloadi16>;
|
|
def LHu : LoadM<0x25, "lhu", zextloadi16>;
|
|
def LW : LoadM<0x23, "lw", load>;
|
|
def SB : StoreM<0x28, "sb", truncstorei8>;
|
|
def SH : StoreM<0x29, "sh", truncstorei16>;
|
|
def SW : StoreM<0x2b, "sw", store>;
|
|
|
|
/// Load-linked, Store-conditional
|
|
let hasDelaySlot = 1 in
|
|
def LL : FI<0x30, (outs CPURegs:$dst), (ins mem:$addr),
|
|
"ll\t$dst, $addr", [], IILoad>;
|
|
let Constraints = "$src = $dst" in
|
|
def SC : FI<0x38, (outs CPURegs:$dst), (ins CPURegs:$src, mem:$addr),
|
|
"sc\t$src, $addr", [], IIStore>;
|
|
|
|
/// Jump and Branch Instructions
|
|
def J : JumpFJ<0x02, "j">;
|
|
def JR : JumpFR<0x00, 0x08, "jr">;
|
|
def JAL : JumpLink<0x03, "jal">;
|
|
def JALR : JumpLinkReg<0x00, 0x09, "jalr">;
|
|
def BEQ : CBranch<0x04, "beq", seteq>;
|
|
def BNE : CBranch<0x05, "bne", setne>;
|
|
|
|
let rt=1 in
|
|
def BGEZ : CBranchZero<0x01, "bgez", setge>;
|
|
|
|
let rt=0 in {
|
|
def BGTZ : CBranchZero<0x07, "bgtz", setgt>;
|
|
def BLEZ : CBranchZero<0x07, "blez", setle>;
|
|
def BLTZ : CBranchZero<0x01, "bltz", setlt>;
|
|
}
|
|
|
|
def BGEZAL : BranchLink<"bgezal">;
|
|
def BLTZAL : BranchLink<"bltzal">;
|
|
|
|
let isReturn=1, isTerminator=1, hasDelaySlot=1,
|
|
isBarrier=1, hasCtrlDep=1, rs=0, rt=0, shamt=0 in
|
|
def RET : FR <0x00, 0x02, (outs), (ins CPURegs:$target),
|
|
"jr\t$target", [(MipsRet CPURegs:$target)], IIBranch>;
|
|
|
|
/// Multiply and Divide Instructions.
|
|
def MULT : Mul<0x18, "mult", IIImul>;
|
|
def MULTu : Mul<0x19, "multu", IIImul>;
|
|
def SDIV : Div<MipsDivRem, 0x1a, "div", IIIdiv>;
|
|
def UDIV : Div<MipsDivRemU, 0x1b, "divu", IIIdiv>;
|
|
|
|
let Defs = [HI] in
|
|
def MTHI : MoveToLOHI<0x11, "mthi">;
|
|
let Defs = [LO] in
|
|
def MTLO : MoveToLOHI<0x13, "mtlo">;
|
|
|
|
let Uses = [HI] in
|
|
def MFHI : MoveFromLOHI<0x10, "mfhi">;
|
|
let Uses = [LO] in
|
|
def MFLO : MoveFromLOHI<0x12, "mflo">;
|
|
|
|
/// Sign Ext In Register Instructions.
|
|
let Predicates = [HasSEInReg] in {
|
|
let shamt = 0x10, rs = 0 in
|
|
def SEB : SignExtInReg<0x21, "seb", i8>;
|
|
|
|
let shamt = 0x18, rs = 0 in
|
|
def SEH : SignExtInReg<0x20, "seh", i16>;
|
|
}
|
|
|
|
/// Count Leading
|
|
def CLZ : CountLeading<0b100000, "clz",
|
|
[(set CPURegs:$dst, (ctlz CPURegs:$src))]>;
|
|
def CLO : CountLeading<0b100001, "clo",
|
|
[(set CPURegs:$dst, (ctlz (not CPURegs:$src)))]>;
|
|
|
|
/// Byte Swap
|
|
let Predicates = [HasSwap] in {
|
|
let shamt = 0x3, rs = 0 in
|
|
def WSBW : ByteSwap<0x20, "wsbw">;
|
|
}
|
|
|
|
/// Conditional Move
|
|
def MIPS_CMOV_ZERO : PatLeaf<(i32 0)>;
|
|
def MIPS_CMOV_NZERO : PatLeaf<(i32 1)>;
|
|
|
|
// Conditional moves:
|
|
// These instructions are expanded in
|
|
// MipsISelLowering::EmitInstrWithCustomInserter if target does not have
|
|
// conditional move instructions.
|
|
// flag:int, data:int
|
|
let usesCustomInserter = 1, shamt = 0, Constraints = "$F = $dst" in
|
|
class CondMovIntInt<bits<6> funct, string instr_asm> :
|
|
FR<0, funct, (outs CPURegs:$dst),
|
|
(ins CPURegs:$T, CPURegs:$cond, CPURegs:$F),
|
|
!strconcat(instr_asm, "\t$dst, $T, $cond"), [], NoItinerary>;
|
|
|
|
def MOVZ_I : CondMovIntInt<0x0a, "movz">;
|
|
def MOVN_I : CondMovIntInt<0x0b, "movn">;
|
|
|
|
/// No operation
|
|
let addr=0 in
|
|
def NOP : FJ<0, (outs), (ins), "nop", [], IIAlu>;
|
|
|
|
// FrameIndexes are legalized when they are operands from load/store
|
|
// instructions. The same not happens for stack address copies, so an
|
|
// add op with mem ComplexPattern is used and the stack address copy
|
|
// can be matched. It's similar to Sparc LEA_ADDRi
|
|
def LEA_ADDiu : EffectiveAddress<"addiu\t$dst, ${addr:stackloc}">;
|
|
|
|
// DynAlloc node points to dynamically allocated stack space.
|
|
// $sp is added to the list of implicitly used registers to prevent dead code
|
|
// elimination from removing instructions that modify $sp.
|
|
let Uses = [SP] in
|
|
def DynAlloc : EffectiveAddress<"addiu\t$dst, ${addr:stackloc}">;
|
|
|
|
// MADD*/MSUB*
|
|
def MADD : MArithR<0, "madd", MipsMAdd, 1>;
|
|
def MADDU : MArithR<1, "maddu", MipsMAddu, 1>;
|
|
def MSUB : MArithR<4, "msub", MipsMSub>;
|
|
def MSUBU : MArithR<5, "msubu", MipsMSubu>;
|
|
|
|
// MUL is a assembly macro in the current used ISAs. In recent ISA's
|
|
// it is a real instruction.
|
|
def MUL : ArithR<0x1c, 0x02, "mul", mul, IIImul, 1>, Requires<[IsMips32]>;
|
|
|
|
def RDHWR : ReadHardware;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Arbitrary patterns that map to one or more instructions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Small immediates
|
|
def : Pat<(i32 immSExt16:$in),
|
|
(ADDiu ZERO, imm:$in)>;
|
|
def : Pat<(i32 immZExt16:$in),
|
|
(ORi ZERO, imm:$in)>;
|
|
|
|
// Arbitrary immediates
|
|
def : Pat<(i32 imm:$imm),
|
|
(ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
|
|
|
|
// Carry patterns
|
|
def : Pat<(subc CPURegs:$lhs, CPURegs:$rhs),
|
|
(SUBu CPURegs:$lhs, CPURegs:$rhs)>;
|
|
def : Pat<(addc CPURegs:$lhs, CPURegs:$rhs),
|
|
(ADDu CPURegs:$lhs, CPURegs:$rhs)>;
|
|
def : Pat<(addc CPURegs:$src, immSExt16:$imm),
|
|
(ADDiu CPURegs:$src, imm:$imm)>;
|
|
|
|
// Call
|
|
def : Pat<(MipsJmpLink (i32 tglobaladdr:$dst)),
|
|
(JAL tglobaladdr:$dst)>;
|
|
def : Pat<(MipsJmpLink (i32 texternalsym:$dst)),
|
|
(JAL texternalsym:$dst)>;
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//def : Pat<(MipsJmpLink CPURegs:$dst),
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// (JALR CPURegs:$dst)>;
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// hi/lo relocs
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def : Pat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
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def : Pat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
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def : Pat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)),
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(ADDiu CPURegs:$hi, tglobaladdr:$lo)>;
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def : Pat<(add CPURegs:$hi, (MipsLo tblockaddress:$lo)),
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(ADDiu CPURegs:$hi, tblockaddress:$lo)>;
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def : Pat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
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def : Pat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)),
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(ADDiu CPURegs:$hi, tjumptable:$lo)>;
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def : Pat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
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def : Pat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)),
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(ADDiu CPURegs:$hi, tconstpool:$lo)>;
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// gp_rel relocs
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def : Pat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)),
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(ADDiu CPURegs:$gp, tglobaladdr:$in)>;
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def : Pat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)),
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(ADDiu CPURegs:$gp, tconstpool:$in)>;
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// tlsgd
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def : Pat<(add CPURegs:$gp, (MipsTlsGd tglobaltlsaddr:$in)),
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(ADDiu CPURegs:$gp, tglobaltlsaddr:$in)>;
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// tprel hi/lo
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def : Pat<(MipsTprelHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
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def : Pat<(add CPURegs:$hi, (MipsTprelLo tglobaltlsaddr:$lo)),
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(ADDiu CPURegs:$hi, tglobaltlsaddr:$lo)>;
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// wrapper_pic
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class WrapperPICPat<SDNode node>:
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Pat<(MipsWrapperPIC node:$in),
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(ADDiu GP, node:$in)>;
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def : WrapperPICPat<tglobaladdr>;
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def : WrapperPICPat<tconstpool>;
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def : WrapperPICPat<texternalsym>;
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def : WrapperPICPat<tblockaddress>;
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def : WrapperPICPat<tjumptable>;
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// Mips does not have "not", so we expand our way
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def : Pat<(not CPURegs:$in),
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(NOR CPURegs:$in, ZERO)>;
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// extended load and stores
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def : Pat<(extloadi1 addr:$src), (LBu addr:$src)>;
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def : Pat<(extloadi8 addr:$src), (LBu addr:$src)>;
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def : Pat<(extloadi16 addr:$src), (LHu addr:$src)>;
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// peepholes
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def : Pat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
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// brcond patterns
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def : Pat<(brcond (setne CPURegs:$lhs, 0), bb:$dst),
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(BNE CPURegs:$lhs, ZERO, bb:$dst)>;
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def : Pat<(brcond (seteq CPURegs:$lhs, 0), bb:$dst),
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(BEQ CPURegs:$lhs, ZERO, bb:$dst)>;
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def : Pat<(brcond (setge CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
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(BEQ (SLT CPURegs:$lhs, CPURegs:$rhs), ZERO, bb:$dst)>;
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def : Pat<(brcond (setuge CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
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(BEQ (SLTu CPURegs:$lhs, CPURegs:$rhs), ZERO, bb:$dst)>;
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def : Pat<(brcond (setge CPURegs:$lhs, immSExt16:$rhs), bb:$dst),
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(BEQ (SLTi CPURegs:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
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def : Pat<(brcond (setuge CPURegs:$lhs, immSExt16:$rhs), bb:$dst),
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(BEQ (SLTiu CPURegs:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
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def : Pat<(brcond (setle CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
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(BEQ (SLT CPURegs:$rhs, CPURegs:$lhs), ZERO, bb:$dst)>;
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def : Pat<(brcond (setule CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
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(BEQ (SLTu CPURegs:$rhs, CPURegs:$lhs), ZERO, bb:$dst)>;
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def : Pat<(brcond CPURegs:$cond, bb:$dst),
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(BNE CPURegs:$cond, ZERO, bb:$dst)>;
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// select patterns
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multiclass MovzPats<RegisterClass RC, Instruction MOVZInst> {
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def : Pat<(select (setge CPURegs:$lhs, CPURegs:$rhs), RC:$T, RC:$F),
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(MOVZInst RC:$T, (SLT CPURegs:$lhs, CPURegs:$rhs), RC:$F)>;
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def : Pat<(select (setuge CPURegs:$lhs, CPURegs:$rhs), RC:$T, RC:$F),
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(MOVZInst RC:$T, (SLTu CPURegs:$lhs, CPURegs:$rhs), RC:$F)>;
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def : Pat<(select (setge CPURegs:$lhs, immSExt16:$rhs), RC:$T, RC:$F),
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(MOVZInst RC:$T, (SLTi CPURegs:$lhs, immSExt16:$rhs), RC:$F)>;
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def : Pat<(select (setuge CPURegs:$lh, immSExt16:$rh), RC:$T, RC:$F),
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(MOVZInst RC:$T, (SLTiu CPURegs:$lh, immSExt16:$rh), RC:$F)>;
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def : Pat<(select (setle CPURegs:$lhs, CPURegs:$rhs), RC:$T, RC:$F),
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(MOVZInst RC:$T, (SLT CPURegs:$rhs, CPURegs:$lhs), RC:$F)>;
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def : Pat<(select (setule CPURegs:$lhs, CPURegs:$rhs), RC:$T, RC:$F),
|
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(MOVZInst RC:$T, (SLTu CPURegs:$rhs, CPURegs:$lhs), RC:$F)>;
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def : Pat<(select (seteq CPURegs:$lhs, CPURegs:$rhs), RC:$T, RC:$F),
|
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(MOVZInst RC:$T, (XOR CPURegs:$lhs, CPURegs:$rhs), RC:$F)>;
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def : Pat<(select (seteq CPURegs:$lhs, 0), RC:$T, RC:$F),
|
|
(MOVZInst RC:$T, CPURegs:$lhs, RC:$F)>;
|
|
}
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|
|
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multiclass MovnPats<RegisterClass RC, Instruction MOVNInst> {
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|
def : Pat<(select (setne CPURegs:$lhs, CPURegs:$rhs), RC:$T, RC:$F),
|
|
(MOVNInst RC:$T, (XOR CPURegs:$lhs, CPURegs:$rhs), RC:$F)>;
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|
def : Pat<(select CPURegs:$cond, RC:$T, RC:$F),
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|
(MOVNInst RC:$T, CPURegs:$cond, RC:$F)>;
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|
def : Pat<(select (setne CPURegs:$lhs, 0), RC:$T, RC:$F),
|
|
(MOVNInst RC:$T, CPURegs:$lhs, RC:$F)>;
|
|
}
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|
|
|
defm : MovzPats<CPURegs, MOVZ_I>;
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|
defm : MovnPats<CPURegs, MOVN_I>;
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|
|
|
// setcc patterns
|
|
def : Pat<(seteq CPURegs:$lhs, CPURegs:$rhs),
|
|
(SLTu (XOR CPURegs:$lhs, CPURegs:$rhs), 1)>;
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def : Pat<(setne CPURegs:$lhs, CPURegs:$rhs),
|
|
(SLTu ZERO, (XOR CPURegs:$lhs, CPURegs:$rhs))>;
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def : Pat<(setle CPURegs:$lhs, CPURegs:$rhs),
|
|
(XORi (SLT CPURegs:$rhs, CPURegs:$lhs), 1)>;
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def : Pat<(setule CPURegs:$lhs, CPURegs:$rhs),
|
|
(XORi (SLTu CPURegs:$rhs, CPURegs:$lhs), 1)>;
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|
|
def : Pat<(setgt CPURegs:$lhs, CPURegs:$rhs),
|
|
(SLT CPURegs:$rhs, CPURegs:$lhs)>;
|
|
def : Pat<(setugt CPURegs:$lhs, CPURegs:$rhs),
|
|
(SLTu CPURegs:$rhs, CPURegs:$lhs)>;
|
|
|
|
def : Pat<(setge CPURegs:$lhs, CPURegs:$rhs),
|
|
(XORi (SLT CPURegs:$lhs, CPURegs:$rhs), 1)>;
|
|
def : Pat<(setuge CPURegs:$lhs, CPURegs:$rhs),
|
|
(XORi (SLTu CPURegs:$lhs, CPURegs:$rhs), 1)>;
|
|
|
|
def : Pat<(setge CPURegs:$lhs, immSExt16:$rhs),
|
|
(XORi (SLTi CPURegs:$lhs, immSExt16:$rhs), 1)>;
|
|
def : Pat<(setuge CPURegs:$lhs, immSExt16:$rhs),
|
|
(XORi (SLTiu CPURegs:$lhs, immSExt16:$rhs), 1)>;
|
|
|
|
// select MipsDynAlloc
|
|
def : Pat<(MipsDynAlloc addr:$f), (DynAlloc addr:$f)>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Floating Point Support
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
include "MipsInstrFPU.td"
|
|
|