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96f1d9ee4d
llvm-mirror/test/MC/AMDGPU
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Sam Kolton 96f1d9ee4d [AMDGPU] Assembler: Support DPP instructions. 
Supprot DPP syntax as used in SP3 (except several operands syntax).
Added dpp-specific operands in td-files.
Added DPP flag to TSFlags to determine if instruction is dpp in InstPrinter.
Support for VOP2 DPP instructions in td-files.
Some tests for DPP instructions.

ToDo:
  - VOP2bInst:
    - vcc is considered as operand
    - AsmMatcher doesn't apply mnemonic aliases when parsing operands
  - v_mac_f32
  - v_nop
  - disable instructions with 64-bit operands
  - change dpp_ctrl assembler representation to conform sp3

Review: http://reviews.llvm.org/D17804
llvm-svn: 263008
2016-03-09 12:29:31 +00:00
..
buffer_wbinv1l_vol_vi.s AMDGPU: Add cache invalidation instructions. 2015-09-24 19:52:21 +00:00
ds-err.s
ds.s [AMDGPU] [llvm-mc] [VI] Fix encoding of LDS/GDS instructions. 2016-02-22 19:17:53 +00:00
flat-scratch.s AMDGPU/SI: Fix encoding for FLAT_SCRATCH registers on VI 2015-12-21 18:44:27 +00:00
flat.s [TableGen] AsmMatcher: Skip optional operands in the midle of instruction if it is not present 2016-03-01 08:34:43 +00:00
hsa_code_object_isa_noargs.s
hsa-text.s AMDGPU/SI: Use .hsatext section instead of .text for HSA 2015-09-25 21:41:28 +00:00
hsa.s AMDGPU/SI: Emit HSA kernels with symbol type STT_AMDGPU_HSA_KERNEL 2015-11-06 11:45:14 +00:00
lit.local.cfg
mimg.s AMDGPU/SI: add llvm.amdgcn.image.atomic.* intrinsics 2016-03-04 10:39:50 +00:00
mubuf.s [TableGen] AsmMatcher: Skip optional operands in the midle of instruction if it is not present 2016-03-01 08:34:43 +00:00
out-of-range-registers.s AMDGPU: Fix asserts on invalid register ranges 2015-11-03 22:50:32 +00:00
smem.s AMDGPU: Add s_dcache_* instructions 2015-09-24 19:52:27 +00:00
smrd-err.s AMDGPU: Disallow s[102:103] on VI in assembler 2015-11-05 03:11:27 +00:00
smrd.s AMDGPU: Implement readcyclecounter 2016-02-27 08:53:46 +00:00
sop1-err.s AMDGPU: Disallow s[102:103] on VI in assembler 2015-11-05 03:11:27 +00:00
sop1.s [AMDGPU] Assembler: Fix s_setpc_b64 2016-03-09 10:56:19 +00:00
sop2.s [AMDGPU] Fix operands of S_BFE_U64 and S_BFM_B64 2016-02-23 09:19:14 +00:00
sopc.s
sopk.s
sopp.s AMDGPU: waitcnt operand fixes 2016-01-28 17:13:44 +00:00
vop1.s AMDGPU/SI: Add 64-bit versions of v_nop and v_clrexcp 2015-10-06 15:57:53 +00:00
vop2-err.s AMDGPU/SI: Fix input vcc operand for VOP2b instructions 2015-09-08 21:15:00 +00:00
vop2.s AMDGPU/SI: Fix input vcc operand for VOP2b instructions 2015-09-08 21:15:00 +00:00
vop3-errs.s [AMDGPU][llvm-mc] Support for 32-bit inline literals 2016-02-22 19:17:56 +00:00
vop3-vop1-nosrc.s AMDGPU/SI: Add 64-bit versions of v_nop and v_clrexcp 2015-10-06 15:57:53 +00:00
vop3.s [AMDGPU] Assembler: Support abs() syntax. 2016-03-09 11:03:21 +00:00
vop_dpp.s [AMDGPU] Assembler: Support DPP instructions. 2016-03-09 12:29:31 +00:00
vopc-errs.s AMDGPU/SI: Use InstAlias instead of MnemonicAlias for VOPC instructions 2015-08-07 22:00:56 +00:00
vopc.s AMDGPU/SI: Use InstAlias instead of MnemonicAlias for VOPC instructions 2015-08-07 22:00:56 +00:00