Piotr Sobczak 97e89dc154 [AMDGPU] Rename amdgcn_wwm to amdgcn_strict_wwm ... * Introduce the new intrinsic amdgcn_strict_wwm * Deprecate the old intrinsic amdgcn_wwm The change is done for consistency as the "strict" prefix will become an important, distinguishing factor between amdgcn_wqm and amdgcn_strictwqm in the future. The "strict" prefix indicates that inactive lanes do not take part in control flow, specifically an inactive lane enabled by a strict mode will always be enabled irrespective of control flow decisions. The amdgcn_wwm will be removed, but doing so in two steps gives users time to switch to the new name at their own pace. Reviewed By: critson Differential Revision: https://reviews.llvm.org/D96257		2021-03-03 09:33:57 +01:00
..
AsmParser	[AMDGPU] Update s_sendmsg messages	2021-02-24 13:07:00 +00:00
Disassembler
MCTargetDesc	[AMDGPU][MC][GFX9+] Corrected encoding of op_sel_hi for unused operands in VOP3P	2021-03-02 13:02:25 +03:00
TargetInfo
Utils	AMDGPU: Add even aligned VGPR/AGPR register classes	2021-02-24 14:49:37 -05:00
AMDGPU.h
AMDGPU.td
AMDGPUAliasAnalysis.cpp
AMDGPUAliasAnalysis.h
AMDGPUAlwaysInlinePass.cpp
AMDGPUAnnotateKernelFeatures.cpp
AMDGPUAnnotateUniformValues.cpp
AMDGPUArgumentUsageInfo.cpp
AMDGPUArgumentUsageInfo.h
AMDGPUAsmPrinter.cpp
AMDGPUAsmPrinter.h
AMDGPUAtomicOptimizer.cpp	[AMDGPU] Rename amdgcn_wwm to amdgcn_strict_wwm	2021-03-03 09:33:57 +01:00
AMDGPUCallingConv.td
AMDGPUCallLowering.cpp	GlobalISel: Merge and cleanup more AMDGPU call lowering code	2021-03-02 17:31:13 -05:00
AMDGPUCallLowering.h	GlobalISel: Merge and cleanup more AMDGPU call lowering code	2021-03-02 17:31:13 -05:00
AMDGPUCodeGenPrepare.cpp
AMDGPUCombine.td
AMDGPUExportClustering.cpp
AMDGPUExportClustering.h
AMDGPUFeatures.td
AMDGPUFixFunctionBitcasts.cpp
AMDGPUFrameLowering.cpp
AMDGPUFrameLowering.h
AMDGPUGenRegisterBankInfo.def
AMDGPUGISel.td
AMDGPUGlobalISelUtils.cpp
AMDGPUGlobalISelUtils.h
AMDGPUHSAMetadataStreamer.cpp
AMDGPUHSAMetadataStreamer.h
AMDGPUInstCombineIntrinsic.cpp
AMDGPUInstrInfo.cpp
AMDGPUInstrInfo.h
AMDGPUInstrInfo.td
AMDGPUInstructions.td
AMDGPUInstructionSelector.cpp	[AMDGPU] Rename amdgcn_wwm to amdgcn_strict_wwm	2021-03-03 09:33:57 +01:00
AMDGPUInstructionSelector.h	[AArch64][GlobalISel] Enable use of the optsize predicate in the selector.	2021-03-02 12:55:51 -08:00
AMDGPUISelDAGToDAG.cpp	[AMDGPU] Rename amdgcn_wwm to amdgcn_strict_wwm	2021-03-03 09:33:57 +01:00
AMDGPUISelLowering.cpp	[AMDGPU][SelectionDAG] Don't combine uniform multiplies to MUL_[UI]24	2021-02-23 15:39:19 +00:00
AMDGPUISelLowering.h
AMDGPULateCodeGenPrepare.cpp
AMDGPULegalizerInfo.cpp	[AMDGPU] Better codegen for i64 bitreverse	2021-02-26 15:51:36 +00:00
AMDGPULegalizerInfo.h
AMDGPULibCalls.cpp
AMDGPULibFunc.cpp
AMDGPULibFunc.h
AMDGPULowerIntrinsics.cpp
AMDGPULowerKernelArguments.cpp
AMDGPULowerKernelAttributes.cpp
AMDGPUMachineCFGStructurizer.cpp
AMDGPUMachineFunction.cpp
AMDGPUMachineFunction.h
AMDGPUMachineModuleInfo.cpp
AMDGPUMachineModuleInfo.h
AMDGPUMacroFusion.cpp
AMDGPUMacroFusion.h
AMDGPUMCInstLower.cpp
AMDGPUMIRFormatter.cpp
AMDGPUMIRFormatter.h
AMDGPUOpenCLEnqueuedBlockLowering.cpp
AMDGPUPerfHintAnalysis.cpp
AMDGPUPerfHintAnalysis.h
AMDGPUPostLegalizerCombiner.cpp
AMDGPUPreLegalizerCombiner.cpp
AMDGPUPrintfRuntimeBinding.cpp
AMDGPUPromoteAlloca.cpp
AMDGPUPropagateAttributes.cpp
AMDGPUPTNote.h
AMDGPURegBankCombiner.cpp
AMDGPURegisterBankInfo.cpp	[AMDGPU] Rename amdgcn_wwm to amdgcn_strict_wwm	2021-03-03 09:33:57 +01:00
AMDGPURegisterBankInfo.h
AMDGPURegisterBanks.td
AMDGPURewriteOutArguments.cpp
AMDGPUSearchableTables.td
AMDGPUSubtarget.cpp
AMDGPUSubtarget.h
AMDGPUTargetMachine.cpp	[AArch64][GlobalISel] Enable use of the optsize predicate in the selector.	2021-03-02 12:55:51 -08:00
AMDGPUTargetMachine.h
AMDGPUTargetObjectFile.cpp
AMDGPUTargetObjectFile.h
AMDGPUTargetTransformInfo.cpp	[AMDGPU] Do not check max-bb for a single block callee	2021-03-01 19:48:50 -08:00
AMDGPUTargetTransformInfo.h
AMDGPUUnifyDivergentExitNodes.cpp
AMDGPUUnifyMetadata.cpp
AMDILCFGStructurizer.cpp
AMDKernelCodeT.h
BUFInstructions.td
CaymanInstructions.td
CMakeLists.txt
DSInstructions.td
EvergreenInstructions.td
EXPInstructions.td
FLATInstructions.td
GCNDPPCombine.cpp
GCNHazardRecognizer.cpp
GCNHazardRecognizer.h
GCNILPSched.cpp
GCNIterativeScheduler.cpp
GCNIterativeScheduler.h
GCNMinRegStrategy.cpp
GCNNSAReassign.cpp
GCNProcessors.td
GCNRegBankReassign.cpp	[AMDGPU] Set threshold for regbanks reassign pass	2021-02-23 10:22:31 -08:00
GCNRegPressure.cpp
GCNRegPressure.h
GCNSchedStrategy.cpp	[AMDGPU] Avoid second rescheduling for some regions	2021-02-26 12:29:37 -08:00
GCNSchedStrategy.h	[AMDGPU] Avoid second rescheduling for some regions	2021-02-26 12:29:37 -08:00
GCNSubtarget.h	AMDGPU: Add even aligned VGPR/AGPR register classes	2021-02-24 14:49:37 -05:00
InstCombineTables.td
MIMGInstructions.td	[AMDGPU] Rename llvm.amdgcn.msaa.load to llvm.amdgcn.msaa.load.x	2021-03-03 17:30:39 +09:00
R600.td
R600AsmPrinter.cpp
R600AsmPrinter.h
R600ClauseMergePass.cpp
R600ControlFlowFinalizer.cpp
R600Defines.h
R600EmitClauseMarkers.cpp
R600ExpandSpecialInstrs.cpp
R600FrameLowering.cpp
R600FrameLowering.h
R600InstrFormats.td
R600InstrInfo.cpp
R600InstrInfo.h
R600Instructions.td
R600ISelLowering.cpp
R600ISelLowering.h
R600MachineFunctionInfo.cpp
R600MachineFunctionInfo.h
R600MachineScheduler.cpp
R600MachineScheduler.h
R600OpenCLImageTypeLoweringPass.cpp
R600OptimizeVectorRegisters.cpp
R600Packetizer.cpp
R600Processors.td
R600RegisterInfo.cpp
R600RegisterInfo.h
R600RegisterInfo.td
R600Schedule.td
R600Subtarget.h
R700Instructions.td
SIAddIMGInit.cpp
SIAnnotateControlFlow.cpp
SIDefines.h	[AMDGPU][MC][GFX9+] Corrected encoding of op_sel_hi for unused operands in VOP3P	2021-03-02 13:02:25 +03:00
SIFixSGPRCopies.cpp	[AMDGPU] Rename amdgcn_wwm to amdgcn_strict_wwm	2021-03-03 09:33:57 +01:00
SIFixVGPRCopies.cpp
SIFoldOperands.cpp
SIFormMemoryClauses.cpp	AMDGPU: Use kill instruction to hint soft clause live ranges	2021-02-26 18:26:40 -05:00
SIFrameLowering.cpp
SIFrameLowering.h
SIInsertHardClauses.cpp
SIInsertSkips.cpp
SIInsertWaitcnts.cpp
SIInstrFormats.td
SIInstrInfo.cpp	[AMDGPU] Rename amdgcn_wwm to amdgcn_strict_wwm	2021-03-03 09:33:57 +01:00
SIInstrInfo.h	[AMDGPU] Better codegen for i64 bitreverse	2021-02-26 15:51:36 +00:00
SIInstrInfo.td	[AMDGPU] Make OMod explicit for V_CVT_{U,I}*	2021-03-02 13:32:06 -05:00
SIInstructions.td	[AMDGPU] Rename amdgcn_wwm to amdgcn_strict_wwm	2021-03-03 09:33:57 +01:00
SIISelLowering.cpp	[AMDGPU] Simplify SITargetLowering::isSDNodeSourceOfDivergence. NFC.	2021-03-01 14:22:08 +00:00
SIISelLowering.h
SILoadStoreOptimizer.cpp	AMDGPU: Add even aligned VGPR/AGPR register classes	2021-02-24 14:49:37 -05:00
SILowerControlFlow.cpp
SILowerI1Copies.cpp
SILowerSGPRSpills.cpp
SIMachineFunctionInfo.cpp
SIMachineFunctionInfo.h
SIMachineScheduler.cpp
SIMachineScheduler.h
SIMemoryLegalizer.cpp
SIModeRegister.cpp
SIOptimizeExecMasking.cpp
SIOptimizeExecMaskingPreRA.cpp
SIPeepholeSDWA.cpp
SIPostRABundler.cpp	AMDGPU: Use kill instruction to hint soft clause live ranges	2021-02-26 18:26:40 -05:00
SIPreAllocateWWMRegs.cpp	[AMDGPU] Rename amdgcn_wwm to amdgcn_strict_wwm	2021-03-03 09:33:57 +01:00
SIPreEmitPeephole.cpp
SIProgramInfo.cpp
SIProgramInfo.h
SIRegisterInfo.cpp	AMDGPU: Remove special case in shouldCoalesce	2021-02-24 14:49:44 -05:00
SIRegisterInfo.h	AMDGPU: Add even aligned VGPR/AGPR register classes	2021-02-24 14:49:37 -05:00
SIRegisterInfo.td	AMDGPU: Add even aligned VGPR/AGPR register classes	2021-02-24 14:49:37 -05:00
SIRemoveShortExecBranches.cpp
SISchedule.td
SIShrinkInstructions.cpp
SIWholeQuadMode.cpp	[AMDGPU] Rename amdgcn_wwm to amdgcn_strict_wwm	2021-03-03 09:33:57 +01:00
SMInstructions.td
SOPInstructions.td	[AMDGPU] New intrinsic void llvm.amdgcn.s.sethalt(i32)	2021-03-01 14:30:23 +00:00
VIInstrFormats.td
VOP1Instructions.td	[AMDGPU] Make OMod explicit for V_CVT_{U,I}*	2021-03-02 13:32:06 -05:00
VOP2Instructions.td	[AMDGPU] Add selection pattern for v_xnor_b32	2021-02-26 16:41:47 +00:00
VOP3Instructions.td
VOP3PInstructions.td
VOPCInstructions.td
VOPInstructions.td	[AMDGPU][MC][GFX9+] Corrected encoding of op_sel_hi for unused operands in VOP3P	2021-03-02 13:02:25 +03:00