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Some instructions may be removable through processes such as IfConversion, however DefinesPredicate can not be made aware of when this should be considered. This parameter allows DefinesPredicate to distinguish these removable instructions on a per-call basis, allowing for more fine-grained control from processes like ifConversion. Renames DefinesPredicate to ClobbersPredicate, to better reflect it's purpose Differential Revision: https://reviews.llvm.org/D88494
338 lines
14 KiB
C++
338 lines
14 KiB
C++
//===-- R600InstrInfo.h - R600 Instruction Info Interface -------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// Interface definition for R600InstrInfo
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_R600INSTRINFO_H
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#define LLVM_LIB_TARGET_AMDGPU_R600INSTRINFO_H
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#include "R600RegisterInfo.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#define GET_INSTRINFO_HEADER
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#include "R600GenInstrInfo.inc"
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namespace llvm {
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namespace R600InstrFlags {
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enum : uint64_t {
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REGISTER_STORE = UINT64_C(1) << 62,
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REGISTER_LOAD = UINT64_C(1) << 63
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};
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}
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class AMDGPUTargetMachine;
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class DFAPacketizer;
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class MachineFunction;
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class MachineInstr;
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class MachineInstrBuilder;
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class R600Subtarget;
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class R600InstrInfo final : public R600GenInstrInfo {
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private:
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const R600RegisterInfo RI;
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const R600Subtarget &ST;
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std::vector<std::pair<int, unsigned>>
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ExtractSrcs(MachineInstr &MI, const DenseMap<unsigned, unsigned> &PV,
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unsigned &ConstCount) const;
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MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator I,
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unsigned ValueReg, unsigned Address,
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unsigned OffsetReg,
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unsigned AddrChan) const;
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MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator I,
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unsigned ValueReg, unsigned Address,
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unsigned OffsetReg,
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unsigned AddrChan) const;
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public:
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enum BankSwizzle {
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ALU_VEC_012_SCL_210 = 0,
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ALU_VEC_021_SCL_122,
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ALU_VEC_120_SCL_212,
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ALU_VEC_102_SCL_221,
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ALU_VEC_201,
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ALU_VEC_210
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};
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explicit R600InstrInfo(const R600Subtarget &);
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const R600RegisterInfo &getRegisterInfo() const {
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return RI;
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}
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void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
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bool KillSrc) const override;
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bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI) const override;
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bool isReductionOp(unsigned opcode) const;
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bool isCubeOp(unsigned opcode) const;
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/// \returns true if this \p Opcode represents an ALU instruction.
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bool isALUInstr(unsigned Opcode) const;
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bool hasInstrModifiers(unsigned Opcode) const;
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bool isLDSInstr(unsigned Opcode) const;
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bool isLDSRetInstr(unsigned Opcode) const;
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/// \returns true if this \p Opcode represents an ALU instruction or an
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/// instruction that will be lowered in ExpandSpecialInstrs Pass.
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bool canBeConsideredALU(const MachineInstr &MI) const;
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bool isTransOnly(unsigned Opcode) const;
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bool isTransOnly(const MachineInstr &MI) const;
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bool isVectorOnly(unsigned Opcode) const;
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bool isVectorOnly(const MachineInstr &MI) const;
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bool isExport(unsigned Opcode) const;
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bool usesVertexCache(unsigned Opcode) const;
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bool usesVertexCache(const MachineInstr &MI) const;
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bool usesTextureCache(unsigned Opcode) const;
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bool usesTextureCache(const MachineInstr &MI) const;
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bool mustBeLastInClause(unsigned Opcode) const;
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bool usesAddressRegister(MachineInstr &MI) const;
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bool definesAddressRegister(MachineInstr &MI) const;
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bool readsLDSSrcReg(const MachineInstr &MI) const;
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/// \returns The operand Index for the Sel operand given an index to one
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/// of the instruction's src operands.
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int getSelIdx(unsigned Opcode, unsigned SrcIdx) const;
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/// \returns a pair for each src of an ALU instructions.
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/// The first member of a pair is the register id.
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/// If register is ALU_CONST, second member is SEL.
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/// If register is ALU_LITERAL, second member is IMM.
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/// Otherwise, second member value is undefined.
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SmallVector<std::pair<MachineOperand *, int64_t>, 3>
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getSrcs(MachineInstr &MI) const;
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unsigned isLegalUpTo(
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const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
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const std::vector<R600InstrInfo::BankSwizzle> &Swz,
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const std::vector<std::pair<int, unsigned> > &TransSrcs,
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R600InstrInfo::BankSwizzle TransSwz) const;
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bool FindSwizzleForVectorSlot(
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const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
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std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
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const std::vector<std::pair<int, unsigned> > &TransSrcs,
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R600InstrInfo::BankSwizzle TransSwz) const;
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/// Given the order VEC_012 < VEC_021 < VEC_120 < VEC_102 < VEC_201 < VEC_210
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/// returns true and the first (in lexical order) BankSwizzle affectation
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/// starting from the one already provided in the Instruction Group MIs that
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/// fits Read Port limitations in BS if available. Otherwise returns false
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/// and undefined content in BS.
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/// isLastAluTrans should be set if the last Alu of MIs will be executed on
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/// Trans ALU. In this case, ValidTSwizzle returns the BankSwizzle value to
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/// apply to the last instruction.
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/// PV holds GPR to PV registers in the Instruction Group MIs.
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bool fitsReadPortLimitations(const std::vector<MachineInstr *> &MIs,
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const DenseMap<unsigned, unsigned> &PV,
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std::vector<BankSwizzle> &BS,
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bool isLastAluTrans) const;
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/// An instruction group can only access 2 channel pair (either [XY] or [ZW])
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/// from KCache bank on R700+. This function check if MI set in input meet
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/// this limitations
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bool fitsConstReadLimitations(const std::vector<MachineInstr *> &) const;
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/// Same but using const index set instead of MI set.
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bool fitsConstReadLimitations(const std::vector<unsigned>&) const;
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/// Vector instructions are instructions that must fill all
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/// instruction slots within an instruction group.
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bool isVector(const MachineInstr &MI) const;
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bool isMov(unsigned Opcode) const;
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DFAPacketizer *
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CreateTargetScheduleState(const TargetSubtargetInfo &) const override;
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bool reverseBranchCondition(
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SmallVectorImpl<MachineOperand> &Cond) const override;
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bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const override;
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unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
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const DebugLoc &DL,
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int *BytesAdded = nullptr) const override;
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unsigned removeBranch(MachineBasicBlock &MBB,
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int *BytesRemvoed = nullptr) const override;
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bool isPredicated(const MachineInstr &MI) const override;
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bool isPredicable(const MachineInstr &MI) const override;
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bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
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BranchProbability Probability) const override;
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bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
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unsigned ExtraPredCycles,
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BranchProbability Probability) const override ;
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bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
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unsigned NumTCycles, unsigned ExtraTCycles,
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MachineBasicBlock &FMBB,
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unsigned NumFCycles, unsigned ExtraFCycles,
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BranchProbability Probability) const override;
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bool ClobbersPredicate(MachineInstr &MI, std::vector<MachineOperand> &Pred,
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bool SkipDead) const override;
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bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
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MachineBasicBlock &FMBB) const override;
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bool PredicateInstruction(MachineInstr &MI,
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ArrayRef<MachineOperand> Pred) const override;
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unsigned int getPredicationCost(const MachineInstr &) const override;
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unsigned int getInstrLatency(const InstrItineraryData *ItinData,
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const MachineInstr &MI,
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unsigned *PredCost = nullptr) const override;
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bool expandPostRAPseudo(MachineInstr &MI) const override;
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/// Reserve the registers that may be accesed using indirect addressing.
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void reserveIndirectRegisters(BitVector &Reserved,
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const MachineFunction &MF,
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const R600RegisterInfo &TRI) const;
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/// Calculate the "Indirect Address" for the given \p RegIndex and
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/// \p Channel
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///
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/// We model indirect addressing using a virtual address space that can be
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/// accesed with loads and stores. The "Indirect Address" is the memory
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/// address in this virtual address space that maps to the given \p RegIndex
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/// and \p Channel.
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unsigned calculateIndirectAddress(unsigned RegIndex, unsigned Channel) const;
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/// \returns The register class to be used for loading and storing values
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/// from an "Indirect Address" .
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const TargetRegisterClass *getIndirectAddrRegClass() const;
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/// \returns the smallest register index that will be accessed by an indirect
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/// read or write or -1 if indirect addressing is not used by this program.
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int getIndirectIndexBegin(const MachineFunction &MF) const;
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/// \returns the largest register index that will be accessed by an indirect
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/// read or write or -1 if indirect addressing is not used by this program.
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int getIndirectIndexEnd(const MachineFunction &MF) const;
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/// Build instruction(s) for an indirect register write.
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///
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/// \returns The instruction that performs the indirect register write
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MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator I,
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unsigned ValueReg, unsigned Address,
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unsigned OffsetReg) const;
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/// Build instruction(s) for an indirect register read.
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///
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/// \returns The instruction that performs the indirect register read
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MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator I,
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unsigned ValueReg, unsigned Address,
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unsigned OffsetReg) const;
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unsigned getMaxAlusPerClause() const;
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/// buildDefaultInstruction - This function returns a MachineInstr with all
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/// the instruction modifiers initialized to their default values. You can
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/// use this function to avoid manually specifying each instruction modifier
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/// operand when building a new instruction.
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///
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/// \returns a MachineInstr with all the instruction modifiers initialized
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/// to their default values.
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MachineInstrBuilder buildDefaultInstruction(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned Opcode,
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unsigned DstReg,
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unsigned Src0Reg,
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unsigned Src1Reg = 0) const;
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MachineInstr *buildSlotOfVectorInstruction(MachineBasicBlock &MBB,
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MachineInstr *MI,
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unsigned Slot,
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unsigned DstReg) const;
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MachineInstr *buildMovImm(MachineBasicBlock &BB,
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MachineBasicBlock::iterator I,
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unsigned DstReg,
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uint64_t Imm) const;
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MachineInstr *buildMovInstr(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator I,
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unsigned DstReg, unsigned SrcReg) const;
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/// Get the index of Op in the MachineInstr.
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///
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/// \returns -1 if the Instruction does not contain the specified \p Op.
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int getOperandIdx(const MachineInstr &MI, unsigned Op) const;
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/// Get the index of \p Op for the given Opcode.
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///
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/// \returns -1 if the Instruction does not contain the specified \p Op.
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int getOperandIdx(unsigned Opcode, unsigned Op) const;
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/// Helper function for setting instruction flag values.
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void setImmOperand(MachineInstr &MI, unsigned Op, int64_t Imm) const;
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///Add one of the MO_FLAG* flags to the specified \p Operand.
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void addFlag(MachineInstr &MI, unsigned Operand, unsigned Flag) const;
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///Determine if the specified \p Flag is set on this \p Operand.
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bool isFlagSet(const MachineInstr &MI, unsigned Operand, unsigned Flag) const;
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/// \param SrcIdx The register source to set the flag on (e.g src0, src1, src2)
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/// \param Flag The flag being set.
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///
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/// \returns the operand containing the flags for this instruction.
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MachineOperand &getFlagOp(MachineInstr &MI, unsigned SrcIdx = 0,
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unsigned Flag = 0) const;
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/// Clear the specified flag on the instruction.
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void clearFlag(MachineInstr &MI, unsigned Operand, unsigned Flag) const;
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// Helper functions that check the opcode for status information
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bool isRegisterStore(const MachineInstr &MI) const {
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return get(MI.getOpcode()).TSFlags & R600InstrFlags::REGISTER_STORE;
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}
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bool isRegisterLoad(const MachineInstr &MI) const {
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return get(MI.getOpcode()).TSFlags & R600InstrFlags::REGISTER_LOAD;
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}
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unsigned getAddressSpaceForPseudoSourceKind(
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unsigned Kind) const override;
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};
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namespace R600 {
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int getLDSNoRetOp(uint16_t Opcode);
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} //End namespace AMDGPU
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} // End llvm namespace
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#endif
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