Lei Huang 852a9b0475 [PowerPC] Fix incorrectly encoded wait instruction ... Encoding for the wait instruction was wrong. Fix according to ISA 3.0. Differential Revision: https://reviews.llvm.org/D48550 llvm-svn: 335514		2018-06-25 19:28:27 +00:00
..
AArch64	[AArch64] Fix spelling of ICH_ELRSR_EL2 system register	2018-02-06 09:39:04 +00:00
AMDGPU	AMDGPU: Fix v_dot{4, 8}* instruction encoding	2018-05-15 19:32:47 +00:00
ARC	[ARC] Add LImm support for J/JL	2018-04-13 15:10:34 +00:00
ARM	[ARM]Decoding MSR with unpredictable destination register causes an assert	2018-03-06 15:21:19 +00:00
Hexagon	[Hexagon] Remove trailing spaces, NFC	2017-11-22 20:43:00 +00:00
Lanai
Mips	[mips] Correct the predicates of arithmetic and logic instructions.	2018-05-30 11:33:35 +00:00
PowerPC	[PowerPC] Fix incorrectly encoded wait instruction	2018-06-25 19:28:27 +00:00
Sparc
SystemZ	[SystemZ] Add support for IBM z14 processor (3/3)	2017-07-17 17:44:20 +00:00
WebAssembly	[WebAssembly] Modified tablegen defs to have 2 parallel instuction sets.	2018-06-18 21:22:44 +00:00
X86	[X86] Teach disassembler to use %eip instead of %rip when 0x67 prefix is used on a rip-relative address.	2018-06-23 06:03:48 +00:00
XCore