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42 lines
1.4 KiB
TableGen
42 lines
1.4 KiB
TableGen
//=-- SVEInstrFormats.td - AArch64 SVE Instruction classes -*- tablegen -*--=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// AArch64 Scalable Vector Extension (SVE) Instruction Class Definitions.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// SVE Integer Arithmetic - Unpredicated Group.
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//===----------------------------------------------------------------------===//
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class sve_int_bin_cons_arit_0<bits<2> sz8_64, bits<3> opc, string asm,
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ZPRRegOp zprty>
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: I<(outs zprty:$Zd), (ins zprty:$Zn, zprty:$Zm),
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asm, "\t$Zd, $Zn, $Zm",
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"", []>, Sched<[]> {
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bits<5> Zd;
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bits<5> Zm;
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bits<5> Zn;
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let Inst{31-24} = 0b00000100;
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let Inst{23-22} = sz8_64;
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let Inst{21} = 0b1;
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let Inst{20-16} = Zm;
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let Inst{15-13} = 0b000;
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let Inst{12-10} = opc;
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let Inst{9-5} = Zn;
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let Inst{4-0} = Zd;
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}
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multiclass sve_int_bin_cons_arit_0<bits<3> opc, string asm> {
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def _B : sve_int_bin_cons_arit_0<0b00, opc, asm, ZPR8>;
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def _H : sve_int_bin_cons_arit_0<0b01, opc, asm, ZPR16>;
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def _S : sve_int_bin_cons_arit_0<0b10, opc, asm, ZPR32>;
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def _D : sve_int_bin_cons_arit_0<0b11, opc, asm, ZPR64>;
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}
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