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AsmParser
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Reverted r319315 because of unused functions (due to PPR not yet being
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2017-11-29 15:14:39 +00:00 |
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Disassembler
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Reverted r319315 because of unused functions (due to PPR not yet being
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2017-11-29 15:14:39 +00:00 |
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InstPrinter
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[AArch64][SVE] Asm: Add SVE (Z) Register definitions and parsing support
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2017-11-07 16:45:48 +00:00 |
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MCTargetDesc
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[AArch64] Allow using emulated tls on platforms other than ELF
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2017-12-04 09:09:04 +00:00 |
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TargetInfo
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Add backend name to Target to enable runtime info to be fed back into TableGen
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2017-11-15 23:55:44 +00:00 |
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Utils
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[AArch64] Add support for dllimport of values and functions
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2017-10-25 07:25:18 +00:00 |
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AArch64.h
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[AArch64] Avoid SIMD interleaved store instruction for Exynos.
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2017-12-08 00:58:49 +00:00 |
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AArch64.td
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AArch64: Enable AES instruction fusion on Cyclone.
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2017-10-17 21:46:15 +00:00 |
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AArch64A53Fix835769.cpp
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Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layering
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2017-11-08 01:01:31 +00:00 |
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AArch64A57FPLoadBalancing.cpp
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[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.
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2017-12-07 10:40:31 +00:00 |
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AArch64AdvSIMDScalarPass.cpp
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AArch64AsmPrinter.cpp
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Fix a bunch more layering of CodeGen headers that are in Target
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2017-11-17 01:07:10 +00:00 |
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AArch64CallingConvention.h
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Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layering
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2017-11-08 01:01:31 +00:00 |
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AArch64CallingConvention.td
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AArch64: support SwiftCC properly on AAPCS64
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2017-09-22 04:31:44 +00:00 |
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AArch64CallLowering.cpp
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[GlobalISel][IRTranslator] Fix crash during translation of zero sized loads/stores/args/returns.
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2017-11-30 20:06:02 +00:00 |
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AArch64CallLowering.h
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GlobalISel (AArch64): fix ABI at border between GPRs and SP.
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2017-08-21 21:56:11 +00:00 |
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AArch64CleanupLocalDynamicTLSPass.cpp
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fix trivial typos in comments; NFC
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2017-07-03 06:32:59 +00:00 |
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AArch64CollectLOH.cpp
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Fix a bunch more layering of CodeGen headers that are in Target
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2017-11-17 01:07:10 +00:00 |
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AArch64CondBrTuning.cpp
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Fix a bunch more layering of CodeGen headers that are in Target
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2017-11-17 01:07:10 +00:00 |
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AArch64ConditionalCompares.cpp
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[CodeGen] Unify MBB reference format in both MIR and debug output
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2017-12-04 17:18:51 +00:00 |
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AArch64ConditionOptimizer.cpp
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[CodeGen] Unify MBB reference format in both MIR and debug output
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2017-12-04 17:18:51 +00:00 |
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AArch64DeadRegisterDefinitionsPass.cpp
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Fix a bunch more layering of CodeGen headers that are in Target
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2017-11-17 01:07:10 +00:00 |
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AArch64ExpandPseudoInsts.cpp
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Fix a bunch more layering of CodeGen headers that are in Target
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2017-11-17 01:07:10 +00:00 |
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AArch64FalkorHWPFFix.cpp
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[CodeGen] Rename functions PrintReg* to printReg*
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2017-11-28 12:42:37 +00:00 |
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AArch64FastISel.cpp
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[AArch64] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).
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2017-07-25 23:51:02 +00:00 |
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AArch64FrameLowering.cpp
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[CodeGen] Always use printReg to print registers in both MIR and debug
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2017-11-30 16:12:24 +00:00 |
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AArch64FrameLowering.h
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Move TargetFrameLowering.h to CodeGen where it's implemented
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2017-11-03 22:32:11 +00:00 |
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AArch64GenRegisterBankInfo.def
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[AArch64][RegisterBankInfo] Teach instruction mapping about gpr32 -> fpr16 cross copies
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2017-11-18 04:28:56 +00:00 |
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AArch64InstrAtomics.td
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[globalisel][tablegen] Add support for relative AtomicOrderings
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2017-11-30 21:05:59 +00:00 |
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AArch64InstrFormats.td
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[globalisel][tablegen] Import stores and allow GISel to automatically substitute zero regs like WZR/XZR/$zero.
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2017-10-23 18:19:24 +00:00 |
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AArch64InstrInfo.cpp
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Reverted r320229. It broke tests on builder llvm-clang-x86_64-expensive-checks-win.
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2017-12-13 15:26:27 +00:00 |
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AArch64InstrInfo.h
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Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layering
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2017-11-08 01:01:31 +00:00 |
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AArch64InstrInfo.td
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[AArch64] Mark mrs of TPIDR_EL0 (thread pointer) as *having* side effects.
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2017-11-21 18:08:34 +00:00 |
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AArch64InstructionSelector.cpp
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Revert r319691: [globalisel][tablegen] Split atomic load/store into separate opcode and enable for AArch64.
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2017-12-05 05:52:07 +00:00 |
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AArch64ISelDAGToDAG.cpp
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[AArch64] Avoid selecting XZR inline ASM memory operand
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2017-07-14 21:46:16 +00:00 |
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AArch64ISelLowering.cpp
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[AArch64] Do not abort if overflow check does not use EQ or NE.
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2017-12-05 21:33:12 +00:00 |
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AArch64ISelLowering.h
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[ARM][AArch64][DAG] Reenable post-legalize store merge
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2017-12-06 15:30:13 +00:00 |
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AArch64LegalizerInfo.cpp
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Revert r319691: [globalisel][tablegen] Split atomic load/store into separate opcode and enable for AArch64.
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2017-12-05 05:52:07 +00:00 |
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AArch64LegalizerInfo.h
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[aarch64][globalisel] Define G_ATOMIC_CMPXCHG and G_ATOMICRMW_* and make them legal
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2017-11-28 20:21:15 +00:00 |
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AArch64LoadStoreOptimizer.cpp
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[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.
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2017-12-07 10:40:31 +00:00 |
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AArch64MachineFunctionInfo.h
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[AArch64] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).
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2017-07-25 23:51:02 +00:00 |
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AArch64MacroFusion.cpp
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Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layering
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2017-11-08 01:01:31 +00:00 |
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AArch64MacroFusion.h
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Recommit rL305677: [CodeGen] Add generic MacroFusion pass
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2017-06-19 12:53:31 +00:00 |
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AArch64MCInstLower.cpp
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Fix a bunch more layering of CodeGen headers that are in Target
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2017-11-17 01:07:10 +00:00 |
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AArch64MCInstLower.h
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[COFF, ARM64] Add support for Windows ARM64 COFF format
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2017-06-27 23:58:19 +00:00 |
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AArch64PBQPRegAlloc.cpp
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Rename LiveIntervalAnalysis.h to LiveIntervals.h
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2017-12-13 02:51:04 +00:00 |
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AArch64PBQPRegAlloc.h
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[CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).
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2017-06-01 23:25:02 +00:00 |
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AArch64PerfectShuffle.h
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AArch64PromoteConstant.cpp
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[AArch64] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).
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2017-07-25 23:51:02 +00:00 |
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AArch64RedundantCopyElimination.cpp
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[CodeGen] Unify MBB reference format in both MIR and debug output
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2017-12-04 17:18:51 +00:00 |
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AArch64RegisterBankInfo.cpp
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[AArch64] Map G_LOAD on FPR when the definition goes to a copy to FPR
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2017-11-18 04:28:59 +00:00 |
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AArch64RegisterBankInfo.h
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[AArch64][RegisterBankInfo] Add mapping for G_FPEXT.
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2017-11-02 23:38:19 +00:00 |
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AArch64RegisterBanks.td
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[aarch64][globalisel] Register banks and classes should have distinct names.
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2017-10-18 00:12:43 +00:00 |
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AArch64RegisterInfo.cpp
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Move TargetFrameLowering.h to CodeGen where it's implemented
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2017-11-03 22:32:11 +00:00 |
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AArch64RegisterInfo.h
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AArch64: Enable post-ra liveness updates
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2016-12-16 23:55:43 +00:00 |
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AArch64RegisterInfo.td
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Reverted r319315 because of unused functions (due to PPR not yet being
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2017-11-29 15:14:39 +00:00 |
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AArch64SchedA53.td
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[AArch64][SVE] Asm: Set SVE as unsupported feature for existing scheduler models.
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2017-11-07 15:03:11 +00:00 |
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AArch64SchedA57.td
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[AArch64][SVE] Asm: Set SVE as unsupported feature for existing scheduler models.
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2017-11-07 15:03:11 +00:00 |
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AArch64SchedA57WriteRes.td
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[AArch64] Cortex-A57 FDIV/FSQRT scheduling fix (W-unit)
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2016-12-23 12:51:41 +00:00 |
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AArch64SchedCyclone.td
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[AArch64][SVE] Asm: Set SVE as unsupported feature for existing scheduler models.
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2017-11-07 15:03:11 +00:00 |
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AArch64SchedFalkor.td
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[AArch64][SVE] Asm: Set SVE as unsupported feature for existing scheduler models.
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2017-11-07 15:03:11 +00:00 |
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AArch64SchedFalkorDetails.td
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[AArch64][Falkor] Remove some non-existent opcodes from sched detail regexes. NFC.
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2017-06-23 21:59:09 +00:00 |
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AArch64SchedKryo.td
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[AArch64][SVE] Asm: Set SVE as unsupported feature for existing scheduler models.
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2017-11-07 15:03:11 +00:00 |
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AArch64SchedKryoDetails.td
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[AArch64][Kryo] Add missing write latency for LDAXP, LDXP second destination.
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2017-06-19 21:57:42 +00:00 |
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AArch64SchedM1.td
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[AArch64] Adjust the cost model for Exynos M1 and M2
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2017-11-22 22:48:50 +00:00 |
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AArch64SchedThunderX2T99.td
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[AArch64] Improve loop unrolling performance on Cavium T99
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2017-12-09 23:59:55 +00:00 |
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AArch64SchedThunderX.td
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[AArch64][SVE] Asm: Set SVE as unsupported feature for existing scheduler models.
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2017-11-07 15:03:11 +00:00 |
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AArch64Schedule.td
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AArch64SelectionDAGInfo.cpp
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[AArch64] Drive-by cleanup, make this code shorter. NFCI.
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2017-03-22 23:37:58 +00:00 |
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AArch64SelectionDAGInfo.h
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AArch64SIMDInstrOpt.cpp
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[AArch64] Rename AArch64VecorByElementOpt.cpp into AArch64SIMDInstrOpt.cpp to reflect the recently added features.
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2017-12-08 22:04:13 +00:00 |
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AArch64StorePairSuppress.cpp
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Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layering
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2017-11-08 01:01:31 +00:00 |
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AArch64Subtarget.cpp
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[aarch64][globalisel] Define G_ATOMIC_CMPXCHG and G_ATOMICRMW_* and make them legal
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2017-11-28 20:21:15 +00:00 |
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AArch64Subtarget.h
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Fix a bunch more layering of CodeGen headers that are in Target
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2017-11-17 01:07:10 +00:00 |
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AArch64SVEInstrInfo.td
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[AArch64][SVE] Asm: Add support for (ADD|SUB)_ZZZ
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2017-11-07 16:58:13 +00:00 |
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AArch64SystemOperands.td
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[AArch64] IDSAR6 register assembler support
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2017-08-31 08:36:45 +00:00 |
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AArch64TargetMachine.cpp
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[AArch64] Avoid SIMD interleaved store instruction for Exynos.
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2017-12-08 00:58:49 +00:00 |
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AArch64TargetMachine.h
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Revert "TargetMachine: Merge TargetMachine and LLVMTargetMachine"
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2017-10-12 22:57:28 +00:00 |
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AArch64TargetObjectFile.cpp
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Move Object format code to lib/BinaryFormat.
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2017-06-07 03:48:56 +00:00 |
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AArch64TargetObjectFile.h
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Fix a bunch more layering of CodeGen headers that are in Target
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2017-11-17 01:07:10 +00:00 |
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AArch64TargetTransformInfo.cpp
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Fix a bunch more layering of CodeGen headers that are in Target
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2017-11-17 01:07:10 +00:00 |
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AArch64TargetTransformInfo.h
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[AArch64] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).
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2017-07-25 23:51:02 +00:00 |
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CMakeLists.txt
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[AArch64] Rename AArch64VecorByElementOpt.cpp into AArch64SIMDInstrOpt.cpp to reflect the recently added features.
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2017-12-08 22:04:13 +00:00 |
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LLVMBuild.txt
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SVEInstrFormats.td
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Test commit
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2017-11-13 09:57:20 +00:00 |
