Ben Langmuir 9981cd7cfe Partial support for Intel SHA Extensions (sha1rnds4) ... Add basic assembly/disassembly support for the first Intel SHA instruction 'sha1rnds4'. Also includes feature flag, and test cases. Support for the remaining instructions will follow in a separate patch. llvm-svn: 190611		2013-09-12 15:51:31 +00:00
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AArch64	Implement aarch64 neon instruction set AdvSIMD (3V Diff), covering the following 26 instructions,	2013-09-09 02:20:27 +00:00
ARM	Somehow this important part of the patch, where I actually check the Mask,	2013-09-12 14:23:19 +00:00
AsmParser	Improve handling of .file, .include and .incbin directives to	2013-09-05 19:14:26 +00:00
COFF	Fix wrong code offset for unwind code SET_FPREG.	2013-08-27 04:16:16 +00:00
Disassembler	Partial support for Intel SHA Extensions (sha1rnds4)	2013-09-12 15:51:31 +00:00
ELF	[tests] Cleanup initialization of test suffixes.	2013-08-16 00:37:11 +00:00
MachO	Fixed a crash in the integrated assembler for Mach-O when a symbol difference	2013-09-05 20:25:06 +00:00
Markup	MC: Simple example parser for MC assembly markup.	2012-10-31 23:24:13 +00:00
Mips	Add test cases for Mips mthc1/mfhc1 instructions. Add check for odd value of register when PFU is 32 bit.	2013-09-10 09:50:01 +00:00
PowerPC	Mark PPC MFTB and DST (and friends) as deprecated	2013-09-12 14:40:06 +00:00
SystemZ	[SystemZ] Add TM and TMY	2013-09-10 10:20:32 +00:00
X86	Partial support for Intel SHA Extensions (sha1rnds4)	2013-09-12 15:51:31 +00:00