Ben Langmuir 9981cd7cfe Partial support for Intel SHA Extensions (sha1rnds4) ... Add basic assembly/disassembly support for the first Intel SHA instruction 'sha1rnds4'. Also includes feature flag, and test cases. Support for the remaining instructions will follow in a separate patch. llvm-svn: 190611		2013-09-12 15:51:31 +00:00
..
AlignedBundling	[tests] Cleanup initialization of test suffixes.	2013-08-16 00:37:11 +00:00
3DNow.s
2011-09-06-NoNewline.s
address-size.s
avx512-encodings.s	AVX-512: implemented extractelement with variable index.	2013-09-12 08:55:00 +00:00
fde-reloc.s
gnux32-dwarf-gen.s
intel-syntax-2.s
intel-syntax-encoding.s
intel-syntax-hex.s
intel-syntax.s	[ms-inline asm] Support offsets after segment registers	2013-08-27 21:56:17 +00:00
lit.local.cfg	[tests] Cleanup initialization of test suffixes.	2013-08-16 00:37:11 +00:00
padlock.s
shuffle-comments.s
x86_64-avx-clmul-encoding.s
x86_64-avx-encoding.s
x86_64-bmi-encoding.s
x86_64-encoding.s	Partial support for Intel SHA Extensions (sha1rnds4)	2013-09-12 15:51:31 +00:00
x86_64-fma3-encoding.s
x86_64-fma4-encoding.s
x86_64-hle-encoding.s
x86_64-imm-widths.s
x86_64-rand-encoding.s
x86_64-rtm-encoding.s
x86_64-sse4a.s
x86_64-xop-encoding.s
x86_directives.s
x86_errors.s
x86_long_nop.s
x86_nop.s
x86_operands.s
x86-32-avx.s
x86-32-coverage.s	Add test cases for the various instruction alias and Intel syntax fixes that have gone in lately.	2013-07-26 05:39:33 +00:00
x86-32-fma3.s
x86-32-ms-inline-asm.s
x86-32.s	Don't let x86 asm printer use the no operand movsd alias. It should use the normal movsl instead.	2013-07-23 01:50:47 +00:00
x86-64.s	Add test cases for the various instruction alias and Intel syntax fixes that have gone in lately.	2013-07-26 05:39:33 +00:00