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54d9c8726b
llvm-svn: 194425
20 lines
733 B
LLVM
20 lines
733 B
LLVM
;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
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;CHECK: LOG_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;CHECK: MUL NON-IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], PS}}
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;CHECK-NEXT: EXP_IEEE * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
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define void @test(<4 x float> inreg %reg0) #0 {
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%r0 = extractelement <4 x float> %reg0, i32 0
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%r1 = extractelement <4 x float> %reg0, i32 1
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%r2 = call float @llvm.pow.f32( float %r0, float %r1)
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%vec = insertelement <4 x float> undef, float %r2, i32 0
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call void @llvm.R600.store.swizzle(<4 x float> %vec, i32 0, i32 0)
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ret void
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}
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declare float @llvm.pow.f32(float ,float ) readonly
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declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
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attributes #0 = { "ShaderType"="0" }
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