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Summary: GCN ISA supports instructions that can read 16 consecutive dwords from memory through the scalar data cache;
loadstoreVectorizer should take advantage of the wider vector length and pack 16/8 elements of dwords/quadwords.
Author: FarhanaAleen
Reviewed By: rampitec
Subscribers: llvm-commits, AMDGPU
Differential Revision: https://reviews.llvm.org/D44179
llvm-svn: 326910
37 lines
2.0 KiB
LLVM
37 lines
2.0 KiB
LLVM
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
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; Tests whether a load chain of 8 constants gets vectorized into a wider load.
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; FUNC-LABEL: {{^}}constant_load_v8f32:
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; GCN: s_load_dwordx8
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; EG: VTX_READ_128
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; EG: VTX_READ_128
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define amdgpu_kernel void @constant_load_v8f32(float addrspace(4)* noalias nocapture readonly %weights, float addrspace(1)* noalias nocapture %out_ptr) {
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entry:
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%out_ptr.promoted = load float, float addrspace(1)* %out_ptr, align 4
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%tmp = load float, float addrspace(4)* %weights, align 4
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%add = fadd float %tmp, %out_ptr.promoted
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%arrayidx.1 = getelementptr inbounds float, float addrspace(4)* %weights, i64 1
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%tmp1 = load float, float addrspace(4)* %arrayidx.1, align 4
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%add.1 = fadd float %tmp1, %add
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%arrayidx.2 = getelementptr inbounds float, float addrspace(4)* %weights, i64 2
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%tmp2 = load float, float addrspace(4)* %arrayidx.2, align 4
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%add.2 = fadd float %tmp2, %add.1
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%arrayidx.3 = getelementptr inbounds float, float addrspace(4)* %weights, i64 3
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%tmp3 = load float, float addrspace(4)* %arrayidx.3, align 4
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%add.3 = fadd float %tmp3, %add.2
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%arrayidx.4 = getelementptr inbounds float, float addrspace(4)* %weights, i64 4
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%tmp4 = load float, float addrspace(4)* %arrayidx.4, align 4
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%add.4 = fadd float %tmp4, %add.3
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%arrayidx.5 = getelementptr inbounds float, float addrspace(4)* %weights, i64 5
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%tmp5 = load float, float addrspace(4)* %arrayidx.5, align 4
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%add.5 = fadd float %tmp5, %add.4
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%arrayidx.6 = getelementptr inbounds float, float addrspace(4)* %weights, i64 6
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%tmp6 = load float, float addrspace(4)* %arrayidx.6, align 4
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%add.6 = fadd float %tmp6, %add.5
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%arrayidx.7 = getelementptr inbounds float, float addrspace(4)* %weights, i64 7
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%tmp7 = load float, float addrspace(4)* %arrayidx.7, align 4
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%add.7 = fadd float %tmp7, %add.6
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store float %add.7, float addrspace(1)* %out_ptr, align 4
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ret void
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} |