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991f9ea5b7
For the AMDGPU target if a MBB contains exec mask restore preamble, SplitEditor may get state when it cannot insert a spill instruction.
E.g. for a MIR
bb.100:
%1 = S_OR_SAVEEXEC_B64 %2, implicit-def $exec, implicit-def $scc, implicit $exec
and if the regalloc will try to allocate a virtreg to the physreg already assigned to virtreg %1, it should insert spill instruction before the S_OR_SAVEEXEC_B64 instruction.
But it is not possible since can generate incorrect code in terms of exec mask.
The change makes regalloc to ignore such physreg candidates.
Reviewed By: rampitec
Differential Revision: https://reviews.llvm.org/D52052
llvm-svn: 343004
101 lines
3.4 KiB
YAML
101 lines
3.4 KiB
YAML
# REQUIRES: asserts
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# RUN: llc -mtriple=amdgcn--- -verify-machineinstrs -debug-only=regalloc -run-pass=greedy -o /dev/null %s 2>&1 | FileCheck %s
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---
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# Check that physreg candidate is not used since cannot be spilled in a block,
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# e.g. before exec mask preamble
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# CHECK: , cannot spill all interferences.
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name: foo
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tracksRegLiveness: true
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registers:
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- { id: 0, class: sreg_64 }
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- { id: 1100, class: sreg_128 }
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- { id: 1101, class: sreg_128 }
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- { id: 1102, class: sreg_128 }
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- { id: 1103, class: sreg_128 }
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- { id: 1104, class: sreg_128 }
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- { id: 1105, class: sreg_128 }
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- { id: 1106, class: sreg_128 }
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- { id: 1107, class: sreg_128 }
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- { id: 1108, class: sreg_128 }
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- { id: 1109, class: sreg_128 }
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- { id: 1110, class: sreg_128 }
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- { id: 1111, class: sreg_128 }
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- { id: 1112, class: sreg_128 }
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- { id: 1113, class: sreg_128 }
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- { id: 1114, class: sreg_128 }
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- { id: 1115, class: sreg_128 }
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- { id: 1116, class: sreg_128 }
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- { id: 1117, class: sreg_128 }
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- { id: 1118, class: sreg_128 }
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- { id: 1119, class: sreg_128 }
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- { id: 1120, class: sreg_128 }
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- { id: 1121, class: sreg_128 }
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body: |
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bb.0:
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successors: %bb.1
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liveins: $sgpr96_sgpr97, $sgpr98_sgpr99, $sgpr100_sgpr101, $sgpr102_sgpr103
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%0:sreg_64 = COPY $sgpr102_sgpr103
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%1100 = COPY $sgpr100_sgpr101_sgpr102_sgpr103
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%1101 = COPY %1100
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%1102 = COPY %1100
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%1103 = COPY %1100
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%1104 = COPY %1100
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%1105 = COPY %1100
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%1106 = COPY %1100
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%1107 = COPY %1100
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%1108 = COPY %1100
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%1109 = COPY %1100
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%1110 = COPY %1100
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%1111 = COPY %1100
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%1112 = COPY %1100
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%1113 = COPY %1100
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%1114 = COPY %1100
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%1115 = COPY %1100
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%1116 = COPY %1100
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%1117 = COPY %1100
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%1118 = COPY %1100
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%1119 = COPY %1100
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%1120 = COPY %1100
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%1121 = COPY %1100
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S_BRANCH %bb.1
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bb.1:
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liveins: $sgpr96_sgpr97, $sgpr98_sgpr99, $sgpr102_sgpr103
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%0 = S_OR_SAVEEXEC_B64 $sgpr96_sgpr97, implicit-def $exec, implicit-def $scc, implicit $exec
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$exec = S_XOR_B64_term $exec, %0, implicit-def $scc
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SI_MASK_BRANCH %bb.100, implicit $exec
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S_BRANCH %bb.2
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bb.2:
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liveins: $sgpr98_sgpr99, $sgpr102_sgpr103
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%0:sreg_64 = S_OR_SAVEEXEC_B64 $sgpr98_sgpr99, implicit-def $exec, implicit-def $scc, implicit $exec
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$exec = S_XOR_B64_term $exec, %0, implicit-def $scc
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SI_MASK_BRANCH %bb.100, implicit $exec
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S_BRANCH %bb.200
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bb.100:
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liveins: $sgpr102_sgpr103
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%0:sreg_64 = S_OR_SAVEEXEC_B64 $sgpr102_sgpr103, implicit-def $exec, implicit-def $scc, implicit $exec
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$exec = S_XOR_B64_term $exec, %0, implicit-def $scc
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S_BRANCH %bb.200
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bb.200:
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S_CMP_EQ_U64 %1100.sub0_sub1, %1101.sub2_sub3, implicit-def $scc
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S_CMP_EQ_U64 %1102.sub0_sub1, %1103.sub2_sub3, implicit-def $scc
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S_CMP_EQ_U64 %1104.sub0_sub1, %1105.sub2_sub3, implicit-def $scc
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S_CMP_EQ_U64 %1106.sub0_sub1, %1107.sub2_sub3, implicit-def $scc
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S_CMP_EQ_U64 %1108.sub0_sub1, %1109.sub2_sub3, implicit-def $scc
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S_CMP_EQ_U64 %1110.sub0_sub1, %1111.sub2_sub3, implicit-def $scc
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S_CMP_EQ_U64 %1112.sub0_sub1, %1113.sub2_sub3, implicit-def $scc
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S_CMP_EQ_U64 %1114.sub0_sub1, %1115.sub2_sub3, implicit-def $scc
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S_CMP_EQ_U64 %1116.sub0_sub1, %1117.sub2_sub3, implicit-def $scc
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S_CMP_EQ_U64 %1118.sub0_sub1, %1119.sub2_sub3, implicit-def $scc
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S_CMP_EQ_U64 %1120.sub0_sub1, %1121.sub2_sub3, implicit-def $scc
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$vgpr0 = V_MOV_B32_e32 0, implicit $exec
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S_SETPC_B64_return %0, implicit $vgpr0
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...
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