mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-26 12:43:36 +01:00
811 lines
18 KiB
LLVM
811 lines
18 KiB
LLVM
; RUN: llc -march=hexagon < %s | FileCheck %s
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@g0 = common global i8 0, align 1
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@g1 = common global i8 0, align 1
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@g2 = common global i16 0, align 2
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@g3 = common global i16 0, align 2
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@g4 = common global i32 0, align 4
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@g5 = common global i32 0, align 4
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; CHECK-LABEL: f0:
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; CHECK: memb(r{{[0-9]+}}+#0) += #1
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define void @f0() #0 {
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b0:
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%v0 = load i8, i8* @g0, align 1, !tbaa !0
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%v1 = add i8 %v0, 1
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store i8 %v1, i8* @g0, align 1, !tbaa !0
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ret void
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}
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; CHECK-LABEL: f1:
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; CHECK: memb(r{{[0-9]+}}+#0) -= #1
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define void @f1() #0 {
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b0:
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%v0 = load i8, i8* @g0, align 1, !tbaa !0
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%v1 = add i8 %v0, -1
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store i8 %v1, i8* @g0, align 1, !tbaa !0
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ret void
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}
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; CHECK-LABEL: f2:
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; CHECK: memb(r{{[0-9]+}}+#0) += #5
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define void @f2() #0 {
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b0:
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%v0 = load i8, i8* @g0, align 1, !tbaa !0
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%v1 = zext i8 %v0 to i32
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%v2 = add nsw i32 %v1, 5
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%v3 = trunc i32 %v2 to i8
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store i8 %v3, i8* @g0, align 1, !tbaa !0
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ret void
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}
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; CHECK-LABEL: f3:
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; CHECK: memb(r{{[0-9]+}}+#0) -= #5
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define void @f3() #0 {
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b0:
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%v0 = load i8, i8* @g0, align 1, !tbaa !0
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%v1 = zext i8 %v0 to i32
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%v2 = add nsw i32 %v1, 251
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%v3 = trunc i32 %v2 to i8
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store i8 %v3, i8* @g0, align 1, !tbaa !0
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ret void
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}
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; CHECK-LABEL: f4:
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; CHECK: memb(r{{[0-9]+}}+#0) -= #5
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define void @f4() #0 {
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b0:
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%v0 = load i8, i8* @g0, align 1, !tbaa !0
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%v1 = zext i8 %v0 to i32
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%v2 = add nsw i32 %v1, 251
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%v3 = trunc i32 %v2 to i8
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store i8 %v3, i8* @g0, align 1, !tbaa !0
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ret void
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}
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; CHECK-LABEL: f5:
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; CHECK: memb(r{{[0-9]+}}+#0) += #5
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define void @f5() #0 {
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b0:
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%v0 = load i8, i8* @g0, align 1, !tbaa !0
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%v1 = zext i8 %v0 to i32
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%v2 = add nsw i32 %v1, 5
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%v3 = trunc i32 %v2 to i8
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store i8 %v3, i8* @g0, align 1, !tbaa !0
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ret void
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}
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; CHECK-LABEL: f6:
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; CHECK: memb(r{{[0-9]+}}+#0) += r{{[0-9]+}}
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define void @f6(i8 zeroext %a0) #0 {
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b0:
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%v0 = zext i8 %a0 to i32
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%v1 = load i8, i8* @g0, align 1, !tbaa !0
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%v2 = zext i8 %v1 to i32
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%v3 = add nsw i32 %v2, %v0
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%v4 = trunc i32 %v3 to i8
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store i8 %v4, i8* @g0, align 1, !tbaa !0
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ret void
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}
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; CHECK-LABEL: f7:
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; CHECK: memb(r{{[0-9]+}}+#0) -= r{{[0-9]+}}
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define void @f7(i8 zeroext %a0) #0 {
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b0:
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%v0 = zext i8 %a0 to i32
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%v1 = load i8, i8* @g0, align 1, !tbaa !0
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%v2 = zext i8 %v1 to i32
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%v3 = sub nsw i32 %v2, %v0
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%v4 = trunc i32 %v3 to i8
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store i8 %v4, i8* @g0, align 1, !tbaa !0
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ret void
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}
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; CHECK-LABEL: f8:
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; CHECK: memb(r{{[0-9]+}}+#0) |= r{{[0-9]+}}
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define void @f8(i8 zeroext %a0) #0 {
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b0:
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%v0 = load i8, i8* @g0, align 1, !tbaa !0
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%v1 = or i8 %v0, %a0
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store i8 %v1, i8* @g0, align 1, !tbaa !0
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ret void
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}
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; CHECK-LABEL: f9:
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; CHECK: memb(r{{[0-9]+}}+#0) &= r{{[0-9]+}}
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define void @f9(i8 zeroext %a0) #0 {
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b0:
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%v0 = load i8, i8* @g0, align 1, !tbaa !0
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%v1 = and i8 %v0, %a0
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store i8 %v1, i8* @g0, align 1, !tbaa !0
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ret void
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}
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; CHECK-LABEL: f10:
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; CHECK: memb(r{{[0-9]+}}+#0) = clrbit(#5)
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define void @f10() #0 {
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b0:
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%v0 = load i8, i8* @g0, align 1, !tbaa !0
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%v1 = zext i8 %v0 to i32
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%v2 = and i32 %v1, 223
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%v3 = trunc i32 %v2 to i8
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store i8 %v3, i8* @g0, align 1, !tbaa !0
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ret void
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}
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; CHECK-LABEL: f11:
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; CHECK: memb(r{{[0-9]+}}+#0) = setbit(#7)
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define void @f11() #0 {
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b0:
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%v0 = load i8, i8* @g0, align 1, !tbaa !0
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%v1 = zext i8 %v0 to i32
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%v2 = or i32 %v1, 128
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%v3 = trunc i32 %v2 to i8
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store i8 %v3, i8* @g0, align 1, !tbaa !0
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ret void
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}
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; CHECK-LABEL: f12:
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; CHECK: memb(r{{[0-9]+}}+#0) += #1
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define void @f12() #0 {
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b0:
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%v0 = load i8, i8* @g1, align 1, !tbaa !0
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%v1 = add i8 %v0, 1
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store i8 %v1, i8* @g1, align 1, !tbaa !0
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ret void
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}
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; CHECK-LABEL: f13:
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; CHECK: memb(r{{[0-9]+}}+#0) -= #1
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define void @f13() #0 {
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b0:
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%v0 = load i8, i8* @g1, align 1, !tbaa !0
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%v1 = add i8 %v0, -1
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store i8 %v1, i8* @g1, align 1, !tbaa !0
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ret void
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}
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; CHECK-LABEL: f14:
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; CHECK: memb(r{{[0-9]+}}+#0) += #5
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define void @f14() #0 {
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b0:
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%v0 = load i8, i8* @g1, align 1, !tbaa !0
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%v1 = zext i8 %v0 to i32
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%v2 = add nsw i32 %v1, 5
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%v3 = trunc i32 %v2 to i8
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store i8 %v3, i8* @g1, align 1, !tbaa !0
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ret void
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}
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; CHECK-LABEL: f15:
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; CHECK: memb(r{{[0-9]+}}+#0) -= #5
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define void @f15() #0 {
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b0:
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%v0 = load i8, i8* @g1, align 1, !tbaa !0
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%v1 = zext i8 %v0 to i32
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%v2 = add nsw i32 %v1, 251
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%v3 = trunc i32 %v2 to i8
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store i8 %v3, i8* @g1, align 1, !tbaa !0
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ret void
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}
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; CHECK-LABEL: f16:
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; CHECK: memb(r{{[0-9]+}}+#0) -= #5
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define void @f16() #0 {
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b0:
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%v0 = load i8, i8* @g1, align 1, !tbaa !0
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%v1 = zext i8 %v0 to i32
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%v2 = add nsw i32 %v1, 251
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%v3 = trunc i32 %v2 to i8
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store i8 %v3, i8* @g1, align 1, !tbaa !0
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ret void
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}
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; CHECK-LABEL: f17:
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; CHECK: memb(r{{[0-9]+}}+#0) += #5
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define void @f17() #0 {
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b0:
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%v0 = load i8, i8* @g1, align 1, !tbaa !0
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%v1 = zext i8 %v0 to i32
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%v2 = add nsw i32 %v1, 5
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%v3 = trunc i32 %v2 to i8
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store i8 %v3, i8* @g1, align 1, !tbaa !0
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ret void
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}
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; CHECK-LABEL: f18:
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; CHECK: memb(r{{[0-9]+}}+#0) += r{{[0-9]+}}
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define void @f18(i8 signext %a0) #0 {
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b0:
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%v0 = zext i8 %a0 to i32
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%v1 = load i8, i8* @g1, align 1, !tbaa !0
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%v2 = zext i8 %v1 to i32
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%v3 = add nsw i32 %v2, %v0
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%v4 = trunc i32 %v3 to i8
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store i8 %v4, i8* @g1, align 1, !tbaa !0
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ret void
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}
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; CHECK-LABEL: f19:
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; CHECK: memb(r{{[0-9]+}}+#0) -= r{{[0-9]+}}
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define void @f19(i8 signext %a0) #0 {
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b0:
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%v0 = zext i8 %a0 to i32
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%v1 = load i8, i8* @g1, align 1, !tbaa !0
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%v2 = zext i8 %v1 to i32
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%v3 = sub nsw i32 %v2, %v0
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%v4 = trunc i32 %v3 to i8
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store i8 %v4, i8* @g1, align 1, !tbaa !0
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ret void
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}
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; CHECK-LABEL: f20:
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; CHECK: memb(r{{[0-9]+}}+#0) |= r{{[0-9]+}}
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define void @f20(i8 signext %a0) #0 {
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b0:
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%v0 = load i8, i8* @g1, align 1, !tbaa !0
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%v1 = or i8 %v0, %a0
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store i8 %v1, i8* @g1, align 1, !tbaa !0
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ret void
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}
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; CHECK-LABEL: f21:
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; CHECK: memb(r{{[0-9]+}}+#0) &= r{{[0-9]+}}
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define void @f21(i8 signext %a0) #0 {
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b0:
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%v0 = load i8, i8* @g1, align 1, !tbaa !0
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%v1 = and i8 %v0, %a0
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store i8 %v1, i8* @g1, align 1, !tbaa !0
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ret void
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}
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; CHECK-LABEL: f22:
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; CHECK: memb(r{{[0-9]+}}+#0) = clrbit(#5)
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define void @f22() #0 {
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b0:
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%v0 = load i8, i8* @g1, align 1, !tbaa !0
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%v1 = zext i8 %v0 to i32
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%v2 = and i32 %v1, 223
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%v3 = trunc i32 %v2 to i8
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store i8 %v3, i8* @g1, align 1, !tbaa !0
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ret void
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}
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; CHECK-LABEL: f23:
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; CHECK: memb(r{{[0-9]+}}+#0) = setbit(#7)
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define void @f23() #0 {
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b0:
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%v0 = load i8, i8* @g1, align 1, !tbaa !0
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%v1 = zext i8 %v0 to i32
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%v2 = or i32 %v1, 128
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%v3 = trunc i32 %v2 to i8
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store i8 %v3, i8* @g1, align 1, !tbaa !0
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ret void
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}
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; CHECK-LABEL: f24:
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; CHECK: memh(r{{[0-9]+}}+#0) += #1
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define void @f24() #0 {
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b0:
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%v0 = load i16, i16* @g2, align 2, !tbaa !3
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%v1 = add i16 %v0, 1
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store i16 %v1, i16* @g2, align 2, !tbaa !3
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ret void
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}
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; CHECK-LABEL: f25:
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; CHECK: memh(r{{[0-9]+}}+#0) -= #1
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define void @f25() #0 {
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b0:
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%v0 = load i16, i16* @g2, align 2, !tbaa !3
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%v1 = add i16 %v0, -1
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store i16 %v1, i16* @g2, align 2, !tbaa !3
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ret void
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}
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; CHECK-LABEL: f26:
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; CHECK: memh(r{{[0-9]+}}+#0) += #5
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define void @f26() #0 {
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b0:
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%v0 = load i16, i16* @g2, align 2, !tbaa !3
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%v1 = zext i16 %v0 to i32
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%v2 = add nsw i32 %v1, 5
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%v3 = trunc i32 %v2 to i16
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store i16 %v3, i16* @g2, align 2, !tbaa !3
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ret void
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}
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; CHECK-LABEL: f27:
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; CHECK: memh(r{{[0-9]+}}+#0) -= #5
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define void @f27() #0 {
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b0:
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%v0 = load i16, i16* @g2, align 2, !tbaa !3
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%v1 = zext i16 %v0 to i32
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%v2 = add nsw i32 %v1, 65531
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%v3 = trunc i32 %v2 to i16
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store i16 %v3, i16* @g2, align 2, !tbaa !3
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ret void
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}
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; CHECK-LABEL: f28:
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; CHECK: memh(r{{[0-9]+}}+#0) -= #5
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define void @f28() #0 {
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b0:
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%v0 = load i16, i16* @g2, align 2, !tbaa !3
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%v1 = zext i16 %v0 to i32
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%v2 = add nsw i32 %v1, 65531
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%v3 = trunc i32 %v2 to i16
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store i16 %v3, i16* @g2, align 2, !tbaa !3
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ret void
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}
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; CHECK-LABEL: f29:
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; CHECK: memh(r{{[0-9]+}}+#0) += #5
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define void @f29() #0 {
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b0:
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%v0 = load i16, i16* @g2, align 2, !tbaa !3
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|
%v1 = zext i16 %v0 to i32
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%v2 = add nsw i32 %v1, 5
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|
%v3 = trunc i32 %v2 to i16
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store i16 %v3, i16* @g2, align 2, !tbaa !3
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ret void
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|
}
|
|
|
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; CHECK-LABEL: f30:
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; CHECK: memh(r{{[0-9]+}}+#0) += r{{[0-9]+}}
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define void @f30(i16 zeroext %a0) #0 {
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b0:
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%v0 = zext i16 %a0 to i32
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%v1 = load i16, i16* @g2, align 2, !tbaa !3
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|
%v2 = zext i16 %v1 to i32
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|
%v3 = add nsw i32 %v2, %v0
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%v4 = trunc i32 %v3 to i16
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store i16 %v4, i16* @g2, align 2, !tbaa !3
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ret void
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}
|
|
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; CHECK-LABEL: f31:
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; CHECK: memh(r{{[0-9]+}}+#0) -= r{{[0-9]+}}
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define void @f31(i16 zeroext %a0) #0 {
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b0:
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%v0 = zext i16 %a0 to i32
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%v1 = load i16, i16* @g2, align 2, !tbaa !3
|
|
%v2 = zext i16 %v1 to i32
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|
%v3 = sub nsw i32 %v2, %v0
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|
%v4 = trunc i32 %v3 to i16
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store i16 %v4, i16* @g2, align 2, !tbaa !3
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|
ret void
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|
}
|
|
|
|
; CHECK-LABEL: f32:
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; CHECK: memh(r{{[0-9]+}}+#0) |= r{{[0-9]+}}
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define void @f32(i16 zeroext %a0) #0 {
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b0:
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%v0 = load i16, i16* @g2, align 2, !tbaa !3
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|
%v1 = or i16 %v0, %a0
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store i16 %v1, i16* @g2, align 2, !tbaa !3
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ret void
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|
}
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|
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; CHECK-LABEL: f33:
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; CHECK: memh(r{{[0-9]+}}+#0) &= r{{[0-9]+}}
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define void @f33(i16 zeroext %a0) #0 {
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b0:
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%v0 = load i16, i16* @g2, align 2, !tbaa !3
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|
%v1 = and i16 %v0, %a0
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|
store i16 %v1, i16* @g2, align 2, !tbaa !3
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ret void
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|
}
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|
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; CHECK-LABEL: f34:
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|
; CHECK: memh(r{{[0-9]+}}+#0) = clrbit(#5)
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define void @f34() #0 {
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b0:
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%v0 = load i16, i16* @g2, align 2, !tbaa !3
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|
%v1 = zext i16 %v0 to i32
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%v2 = and i32 %v1, 65503
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%v3 = trunc i32 %v2 to i16
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store i16 %v3, i16* @g2, align 2, !tbaa !3
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ret void
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|
}
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|
|
|
; CHECK-LABEL: f35:
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|
; CHECK: memh(r{{[0-9]+}}+#0) = setbit(#7)
|
|
define void @f35() #0 {
|
|
b0:
|
|
%v0 = load i16, i16* @g2, align 2, !tbaa !3
|
|
%v1 = zext i16 %v0 to i32
|
|
%v2 = or i32 %v1, 128
|
|
%v3 = trunc i32 %v2 to i16
|
|
store i16 %v3, i16* @g2, align 2, !tbaa !3
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|
ret void
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|
}
|
|
|
|
; CHECK-LABEL: f36:
|
|
; CHECK: memh(r{{[0-9]+}}+#0) += #1
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|
define void @f36() #0 {
|
|
b0:
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|
%v0 = load i16, i16* @g3, align 2, !tbaa !3
|
|
%v1 = add i16 %v0, 1
|
|
store i16 %v1, i16* @g3, align 2, !tbaa !3
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: f37:
|
|
; CHECK: memh(r{{[0-9]+}}+#0) -= #1
|
|
define void @f37() #0 {
|
|
b0:
|
|
%v0 = load i16, i16* @g3, align 2, !tbaa !3
|
|
%v1 = add i16 %v0, -1
|
|
store i16 %v1, i16* @g3, align 2, !tbaa !3
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: f38:
|
|
; CHECK: memh(r{{[0-9]+}}+#0) += #5
|
|
define void @f38() #0 {
|
|
b0:
|
|
%v0 = load i16, i16* @g3, align 2, !tbaa !3
|
|
%v1 = zext i16 %v0 to i32
|
|
%v2 = add nsw i32 %v1, 5
|
|
%v3 = trunc i32 %v2 to i16
|
|
store i16 %v3, i16* @g3, align 2, !tbaa !3
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: f39:
|
|
; CHECK: memh(r{{[0-9]+}}+#0) -= #5
|
|
define void @f39() #0 {
|
|
b0:
|
|
%v0 = load i16, i16* @g3, align 2, !tbaa !3
|
|
%v1 = zext i16 %v0 to i32
|
|
%v2 = add nsw i32 %v1, 65531
|
|
%v3 = trunc i32 %v2 to i16
|
|
store i16 %v3, i16* @g3, align 2, !tbaa !3
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: f40:
|
|
; CHECK: memh(r{{[0-9]+}}+#0) -= #5
|
|
define void @f40() #0 {
|
|
b0:
|
|
%v0 = load i16, i16* @g3, align 2, !tbaa !3
|
|
%v1 = zext i16 %v0 to i32
|
|
%v2 = add nsw i32 %v1, 65531
|
|
%v3 = trunc i32 %v2 to i16
|
|
store i16 %v3, i16* @g3, align 2, !tbaa !3
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: f41
|
|
; CHECK: memh(r{{[0-9]+}}+#0) += #5
|
|
define void @f41() #0 {
|
|
b0:
|
|
%v0 = load i16, i16* @g3, align 2, !tbaa !3
|
|
%v1 = zext i16 %v0 to i32
|
|
%v2 = add nsw i32 %v1, 5
|
|
%v3 = trunc i32 %v2 to i16
|
|
store i16 %v3, i16* @g3, align 2, !tbaa !3
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: f42
|
|
; CHECK: memh(r{{[0-9]+}}+#0) += r{{[0-9]+}}
|
|
define void @f42(i16 signext %a0) #0 {
|
|
b0:
|
|
%v0 = zext i16 %a0 to i32
|
|
%v1 = load i16, i16* @g3, align 2, !tbaa !3
|
|
%v2 = zext i16 %v1 to i32
|
|
%v3 = add nsw i32 %v2, %v0
|
|
%v4 = trunc i32 %v3 to i16
|
|
store i16 %v4, i16* @g3, align 2, !tbaa !3
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: f43
|
|
; CHECK: memh(r{{[0-9]+}}+#0) -= r{{[0-9]+}}
|
|
define void @f43(i16 signext %a0) #0 {
|
|
b0:
|
|
%v0 = zext i16 %a0 to i32
|
|
%v1 = load i16, i16* @g3, align 2, !tbaa !3
|
|
%v2 = zext i16 %v1 to i32
|
|
%v3 = sub nsw i32 %v2, %v0
|
|
%v4 = trunc i32 %v3 to i16
|
|
store i16 %v4, i16* @g3, align 2, !tbaa !3
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: f44
|
|
; CHECK: memh(r{{[0-9]+}}+#0) |= r{{[0-9]+}}
|
|
define void @f44(i16 signext %a0) #0 {
|
|
b0:
|
|
%v0 = load i16, i16* @g3, align 2, !tbaa !3
|
|
%v1 = or i16 %v0, %a0
|
|
store i16 %v1, i16* @g3, align 2, !tbaa !3
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: f45
|
|
; CHECK: memh(r{{[0-9]+}}+#0) &= r{{[0-9]+}}
|
|
define void @f45(i16 signext %a0) #0 {
|
|
b0:
|
|
%v0 = load i16, i16* @g3, align 2, !tbaa !3
|
|
%v1 = and i16 %v0, %a0
|
|
store i16 %v1, i16* @g3, align 2, !tbaa !3
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: f46
|
|
; CHECK: memh(r{{[0-9]+}}+#0) = clrbit(#5)
|
|
define void @f46() #0 {
|
|
b0:
|
|
%v0 = load i16, i16* @g3, align 2, !tbaa !3
|
|
%v1 = zext i16 %v0 to i32
|
|
%v2 = and i32 %v1, 65503
|
|
%v3 = trunc i32 %v2 to i16
|
|
store i16 %v3, i16* @g3, align 2, !tbaa !3
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: f47
|
|
; CHECK: memh(r{{[0-9]+}}+#0) = setbit(#7)
|
|
define void @f47() #0 {
|
|
b0:
|
|
%v0 = load i16, i16* @g3, align 2, !tbaa !3
|
|
%v1 = zext i16 %v0 to i32
|
|
%v2 = or i32 %v1, 128
|
|
%v3 = trunc i32 %v2 to i16
|
|
store i16 %v3, i16* @g3, align 2, !tbaa !3
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: f48
|
|
; CHECK: memw(r{{[0-9]+}}+#0) += #1
|
|
define void @f48() #0 {
|
|
b0:
|
|
%v0 = load i32, i32* @g4, align 4, !tbaa !5
|
|
%v1 = add nsw i32 %v0, 1
|
|
store i32 %v1, i32* @g4, align 4, !tbaa !5
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: f49
|
|
; CHECK: memw(r{{[0-9]+}}+#0) -= #1
|
|
define void @f49() #0 {
|
|
b0:
|
|
%v0 = load i32, i32* @g4, align 4, !tbaa !5
|
|
%v1 = add nsw i32 %v0, -1
|
|
store i32 %v1, i32* @g4, align 4, !tbaa !5
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: f50
|
|
; CHECK: memw(r{{[0-9]+}}+#0) += #5
|
|
define void @f50() #0 {
|
|
b0:
|
|
%v0 = load i32, i32* @g4, align 4, !tbaa !5
|
|
%v1 = add nsw i32 %v0, 5
|
|
store i32 %v1, i32* @g4, align 4, !tbaa !5
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: f51
|
|
; CHECK: memw(r{{[0-9]+}}+#0) -= #5
|
|
define void @f51() #0 {
|
|
b0:
|
|
%v0 = load i32, i32* @g4, align 4, !tbaa !5
|
|
%v1 = add nsw i32 %v0, -5
|
|
store i32 %v1, i32* @g4, align 4, !tbaa !5
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: f52
|
|
; CHECK: memw(r{{[0-9]+}}+#0) -= #5
|
|
define void @f52() #0 {
|
|
b0:
|
|
%v0 = load i32, i32* @g4, align 4, !tbaa !5
|
|
%v1 = add nsw i32 %v0, -5
|
|
store i32 %v1, i32* @g4, align 4, !tbaa !5
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: f53
|
|
; CHECK: memw(r{{[0-9]+}}+#0) += #5
|
|
define void @f53() #0 {
|
|
b0:
|
|
%v0 = load i32, i32* @g4, align 4, !tbaa !5
|
|
%v1 = add nsw i32 %v0, 5
|
|
store i32 %v1, i32* @g4, align 4, !tbaa !5
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: f54
|
|
; CHECK: memw(r{{[0-9]+}}+#0) += r{{[0-9]+}}
|
|
define void @f54(i32 %a0) #0 {
|
|
b0:
|
|
%v0 = load i32, i32* @g4, align 4, !tbaa !5
|
|
%v1 = add i32 %v0, %a0
|
|
store i32 %v1, i32* @g4, align 4, !tbaa !5
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: f55
|
|
; CHECK: memw(r{{[0-9]+}}+#0) -= r{{[0-9]+}}
|
|
define void @f55(i32 %a0) #0 {
|
|
b0:
|
|
%v0 = load i32, i32* @g4, align 4, !tbaa !5
|
|
%v1 = sub i32 %v0, %a0
|
|
store i32 %v1, i32* @g4, align 4, !tbaa !5
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: f56
|
|
; CHECK: memw(r{{[0-9]+}}+#0) |= r{{[0-9]+}}
|
|
define void @f56(i32 %a0) #0 {
|
|
b0:
|
|
%v0 = load i32, i32* @g4, align 4, !tbaa !5
|
|
%v1 = or i32 %v0, %a0
|
|
store i32 %v1, i32* @g4, align 4, !tbaa !5
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: f57
|
|
; CHECK: memw(r{{[0-9]+}}+#0) &= r{{[0-9]+}}
|
|
define void @f57(i32 %a0) #0 {
|
|
b0:
|
|
%v0 = load i32, i32* @g4, align 4, !tbaa !5
|
|
%v1 = and i32 %v0, %a0
|
|
store i32 %v1, i32* @g4, align 4, !tbaa !5
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: f58
|
|
; CHECK: memw(r{{[0-9]+}}+#0) = clrbit(#5)
|
|
define void @f58() #0 {
|
|
b0:
|
|
%v0 = load i32, i32* @g4, align 4, !tbaa !5
|
|
%v1 = and i32 %v0, -33
|
|
store i32 %v1, i32* @g4, align 4, !tbaa !5
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: f59
|
|
; CHECK: memw(r{{[0-9]+}}+#0) = setbit(#7)
|
|
define void @f59() #0 {
|
|
b0:
|
|
%v0 = load i32, i32* @g4, align 4, !tbaa !5
|
|
%v1 = or i32 %v0, 128
|
|
store i32 %v1, i32* @g4, align 4, !tbaa !5
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: f60
|
|
; CHECK: memw(r{{[0-9]+}}+#0) += #1
|
|
define void @f60() #0 {
|
|
b0:
|
|
%v0 = load i32, i32* @g5, align 4, !tbaa !5
|
|
%v1 = add i32 %v0, 1
|
|
store i32 %v1, i32* @g5, align 4, !tbaa !5
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: f61
|
|
; CHECK: memw(r{{[0-9]+}}+#0) -= #1
|
|
define void @f61() #0 {
|
|
b0:
|
|
%v0 = load i32, i32* @g5, align 4, !tbaa !5
|
|
%v1 = add i32 %v0, -1
|
|
store i32 %v1, i32* @g5, align 4, !tbaa !5
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: f62
|
|
; CHECK: memw(r{{[0-9]+}}+#0) += #5
|
|
define void @f62() #0 {
|
|
b0:
|
|
%v0 = load i32, i32* @g5, align 4, !tbaa !5
|
|
%v1 = add i32 %v0, 5
|
|
store i32 %v1, i32* @g5, align 4, !tbaa !5
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: f63
|
|
; CHECK: memw(r{{[0-9]+}}+#0) -= #5
|
|
define void @f63() #0 {
|
|
b0:
|
|
%v0 = load i32, i32* @g5, align 4, !tbaa !5
|
|
%v1 = add i32 %v0, -5
|
|
store i32 %v1, i32* @g5, align 4, !tbaa !5
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: f64
|
|
; CHECK: memw(r{{[0-9]+}}+#0) -= #5
|
|
define void @f64() #0 {
|
|
b0:
|
|
%v0 = load i32, i32* @g5, align 4, !tbaa !5
|
|
%v1 = add i32 %v0, -5
|
|
store i32 %v1, i32* @g5, align 4, !tbaa !5
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: f65
|
|
; CHECK: memw(r{{[0-9]+}}+#0) += #5
|
|
define void @f65() #0 {
|
|
b0:
|
|
%v0 = load i32, i32* @g5, align 4, !tbaa !5
|
|
%v1 = add i32 %v0, 5
|
|
store i32 %v1, i32* @g5, align 4, !tbaa !5
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: f66:
|
|
; CHECK: memw(r{{[0-9]+}}+#0) += r{{[0-9]+}}
|
|
define void @f66(i32 %a0) #0 {
|
|
b0:
|
|
%v0 = load i32, i32* @g5, align 4, !tbaa !5
|
|
%v1 = add i32 %v0, %a0
|
|
store i32 %v1, i32* @g5, align 4, !tbaa !5
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: f67:
|
|
; CHECK: memw(r{{[0-9]+}}+#0) -= r{{[0-9]+}}
|
|
define void @f67(i32 %a0) #0 {
|
|
b0:
|
|
%v0 = load i32, i32* @g5, align 4, !tbaa !5
|
|
%v1 = sub i32 %v0, %a0
|
|
store i32 %v1, i32* @g5, align 4, !tbaa !5
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: f68:
|
|
; CHECK: memw(r{{[0-9]+}}+#0) |= r{{[0-9]+}}
|
|
define void @f68(i32 %a0) #0 {
|
|
b0:
|
|
%v0 = load i32, i32* @g5, align 4, !tbaa !5
|
|
%v1 = or i32 %v0, %a0
|
|
store i32 %v1, i32* @g5, align 4, !tbaa !5
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: f69:
|
|
; CHECK: memw(r{{[0-9]+}}+#0) &= r{{[0-9]+}}
|
|
define void @f69(i32 %a0) #0 {
|
|
b0:
|
|
%v0 = load i32, i32* @g5, align 4, !tbaa !5
|
|
%v1 = and i32 %v0, %a0
|
|
store i32 %v1, i32* @g5, align 4, !tbaa !5
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: f70:
|
|
; CHECK: memw(r{{[0-9]+}}+#0) = clrbit(#5)
|
|
define void @f70() #0 {
|
|
b0:
|
|
%v0 = load i32, i32* @g5, align 4, !tbaa !5
|
|
%v1 = and i32 %v0, -33
|
|
store i32 %v1, i32* @g5, align 4, !tbaa !5
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: f71:
|
|
; CHECK: memw(r{{[0-9]+}}+#0) = setbit(#7)
|
|
define void @f71() #0 {
|
|
b0:
|
|
%v0 = load i32, i32* @g5, align 4, !tbaa !5
|
|
%v1 = or i32 %v0, 128
|
|
store i32 %v1, i32* @g5, align 4, !tbaa !5
|
|
ret void
|
|
}
|
|
|
|
attributes #0 = { nounwind }
|
|
|
|
!0 = !{!1, !1, i64 0}
|
|
!1 = !{!"omnipotent char", !2}
|
|
!2 = !{!"Simple C/C++ TBAA"}
|
|
!3 = !{!4, !4, i64 0}
|
|
!4 = !{!"short", !1}
|
|
!5 = !{!6, !6, i64 0}
|
|
!6 = !{!"int", !1}
|