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llvm-mirror/test/CodeGen/Mips/disable-tail-merge.ll
David Blaikie ab043ff680 [opaque pointer type] Add textual IR support for explicit type parameter to load instruction
Essentially the same as the GEP change in r230786.

A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)

import fileinput
import sys
import re

pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")

for line in sys.stdin:
  sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))

Reviewers: rafael, dexonsmith, grosser

Differential Revision: http://reviews.llvm.org/D7649

llvm-svn: 230794
2015-02-27 21:17:42 +00:00

34 lines
810 B
LLVM

; RUN: llc -march=mipsel < %s | FileCheck %s
@g0 = common global i32 0, align 4
@g1 = common global i32 0, align 4
; CHECK: addiu ${{[0-9]+}}, ${{[0-9]+}}, 23
; CHECK: addiu ${{[0-9]+}}, ${{[0-9]+}}, 23
define i32 @test1(i32 %a) {
entry:
%tobool = icmp eq i32 %a, 0
%0 = load i32, i32* @g0, align 4
br i1 %tobool, label %if.else, label %if.then
if.then:
%add = add nsw i32 %0, 1
store i32 %add, i32* @g0, align 4
%1 = load i32, i32* @g1, align 4
%add1 = add nsw i32 %1, 23
br label %if.end
if.else:
%add2 = add nsw i32 %0, 11
store i32 %add2, i32* @g0, align 4
%2 = load i32, i32* @g1, align 4
%add3 = add nsw i32 %2, 23
br label %if.end
if.end:
%storemerge = phi i32 [ %add3, %if.else ], [ %add1, %if.then ]
store i32 %storemerge, i32* @g1, align 4
ret i32 %storemerge
}