Simon Pilgrim 99e3cf65ff Revert: r270973 - [X86][SSE] Replace (V)PMOVSX and (V)PMOVZX integer extension intrinsics with generic IR (llvm) ... llvm-svn: 270976		2016-05-27 09:02:25 +00:00
..
AArch64	[AArch64] Generate rev16/rev32 from bswap + srl when upper bits are known zero.	2016-05-26 19:41:33 +00:00
AMDGPU	AMDGPU/SI: Enable load-store-opt by default.	2016-05-26 19:35:29 +00:00
ARM	[ARM, AArch64] Match additional patterns to ldN instructions	2016-05-19 21:39:00 +00:00
BPF	[BPF] Remove exit-on-error flag in test (PR27767)	2016-05-26 15:23:50 +00:00
Generic	llc: Rework -run-pass option	2016-05-10 01:32:44 +00:00
Hexagon	[Hexagon] Enable the post-RA scheduler	2016-05-26 19:44:28 +00:00
Inputs
Lanai	[lanai] Change reloc to use PIC_ by default and cleanup.	2016-05-20 21:41:53 +00:00
Mips	[mips][mips16] Fix ZERO is not a CPU16Regs register error from the machine verifier.	2016-05-19 10:42:14 +00:00
MIR	Add test/CodeGen/MIR/Hexagon/lit.local.cfg	2016-05-26 18:35:45 +00:00
MSP430
NVPTX	[NVPTX] Added NVVMIntrRange pass	2016-05-26 17:02:56 +00:00
PowerPC	Move and add comments to the top for tailcall-string-rvo.ll	2016-05-25 17:01:09 +00:00
SPARC	[SPARC] Fix 8 and 16-bit atomic load and store.	2016-05-23 20:33:00 +00:00
SystemZ	[SystemZ] Fix register ordering for BinaryRRF instructions	2016-05-18 13:24:57 +00:00
Thumb	ARM: stop emitting blx instructions for most calls on MachO.	2016-05-10 19:17:47 +00:00
Thumb2	ARM: stop emitting blx instructions for most calls on MachO.	2016-05-10 19:17:47 +00:00
WebAssembly	[WebAssembly] Put __stack_pointer in the offset field of loads and stores.	2016-05-24 23:47:41 +00:00
WinEH
X86	Revert: r270973 - [X86][SSE] Replace (V)PMOVSX and (V)PMOVZX integer extension intrinsics with generic IR (llvm)	2016-05-27 09:02:25 +00:00
XCore