Craig Topper 6bfc6b8665 [RISCV] Select vector shl by 1 to a vector add. ... A vector add may be faster than a vector shift. Reviewed By: frasercrmck Differential Revision: https://reviews.llvm.org/D106689		2021-07-27 10:57:28 -07:00
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AsmParser	[RISCV] Teach constant materialization that it can use zext.w at the end with Zba to reduce number of instructions.	2021-07-16 09:35:56 -07:00
Disassembler
MCTargetDesc	[RISCV] Teach RISCVMatInt about cases where it can use LUI+SLLI to replace LUI+ADDI+SLLI for large constants.	2021-07-20 09:22:06 -07:00
TargetInfo
CMakeLists.txt
RISCV.h
RISCV.td
RISCVAsmPrinter.cpp
RISCVCallingConv.td
RISCVCallLowering.cpp
RISCVCallLowering.h
RISCVExpandAtomicPseudoInsts.cpp
RISCVExpandPseudoInsts.cpp
RISCVFrameLowering.cpp	[RISCV] Add FrameSetup/FrameDestroy flag to prologue/epilog instructions.	2021-07-23 11:35:19 +08:00
RISCVFrameLowering.h	[RISCV] Add FrameSetup/FrameDestroy flag to prologue/epilog instructions.	2021-07-23 11:35:19 +08:00
RISCVInsertVSETVLI.cpp	[RISCV] Avoid using x0,x0 vsetvli for vmv.x.s and vfmv.f.s unless we know the sew/lmul ratio is constant.	2021-07-23 09:12:05 -07:00
RISCVInstrFormats.td
RISCVInstrFormatsC.td
RISCVInstrFormatsV.td
RISCVInstrInfo.cpp	[RISCV] Add FrameSetup/FrameDestroy flag to prologue/epilog instructions.	2021-07-23 11:35:19 +08:00
RISCVInstrInfo.h	[RISCV] Add FrameSetup/FrameDestroy flag to prologue/epilog instructions.	2021-07-23 11:35:19 +08:00
RISCVInstrInfo.td	[RISCV] Add custom isel to select (and (srl X, C1), C2) and (and (shl X, C1), C2)	2021-07-20 08:53:55 -07:00
RISCVInstrInfoA.td
RISCVInstrInfoB.td	[RISCV] Optimize multiplication in the zba extension with SH*ADD	2021-07-22 10:28:41 +08:00
RISCVInstrInfoC.td
RISCVInstrInfoD.td	[RISCV] Custom lower (i32 (fptoui/fptosi X)).	2021-07-24 10:50:43 -07:00
RISCVInstrInfoF.td	[RISCV] Custom lower (i32 (fptoui/fptosi X)).	2021-07-24 10:50:43 -07:00
RISCVInstrInfoM.td
RISCVInstrInfoV.td
RISCVInstrInfoVPseudos.td	[RISCV] Use tail agnostic policy for fixed vector vwmacc(u).	2021-07-16 10:41:09 -07:00
RISCVInstrInfoVSDPatterns.td	[RISCV] Select vector shl by 1 to a vector add.	2021-07-27 10:57:28 -07:00
RISCVInstrInfoVVLPatterns.td	[RISCV] Select vector shl by 1 to a vector add.	2021-07-27 10:57:28 -07:00
RISCVInstrInfoZfh.td	[RISCV] Custom lower (i32 (fptoui/fptosi X)).	2021-07-24 10:50:43 -07:00
RISCVInstructionSelector.cpp
RISCVISelDAGToDAG.cpp	[RISCV] Add custom isel to select (and (srl X, C1), C2) and (and (shl X, C1), C2)	2021-07-20 08:53:55 -07:00
RISCVISelDAGToDAG.h	[RISCV] Add custom isel to select (and (srl X, C1), C2) and (and (shl X, C1), C2)	2021-07-20 08:53:55 -07:00
RISCVISelLowering.cpp	[RISCV] Add support for vector saturating add/sub operations	2021-07-27 10:04:14 +01:00
RISCVISelLowering.h	[RISCV] Add support for vector saturating add/sub operations	2021-07-27 10:04:14 +01:00
RISCVLegalizerInfo.cpp
RISCVLegalizerInfo.h
RISCVMachineFunctionInfo.h
RISCVMCInstLower.cpp
RISCVMergeBaseOffset.cpp
RISCVRegisterBankInfo.cpp
RISCVRegisterBankInfo.h
RISCVRegisterBanks.td
RISCVRegisterInfo.cpp
RISCVRegisterInfo.h
RISCVRegisterInfo.td	[RISCV] Make VLEN no greater than 65536	2021-07-17 12:47:46 +08:00
RISCVSchedRocket.td
RISCVSchedSiFive7.td
RISCVSchedule.td
RISCVScheduleB.td
RISCVSubtarget.cpp	[RISCV] Make VLEN no greater than 65536	2021-07-17 12:47:46 +08:00
RISCVSubtarget.h
RISCVSystemOperands.td
RISCVTargetMachine.cpp
RISCVTargetMachine.h
RISCVTargetObjectFile.cpp
RISCVTargetObjectFile.h
RISCVTargetTransformInfo.cpp	[RISCV] Teach constant materialization that it can use zext.w at the end with Zba to reduce number of instructions.	2021-07-16 09:35:56 -07:00
RISCVTargetTransformInfo.h